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cml microcircuits communication semiconductor s cmx990 gmsk packet data modem and rf transceiver ? 2008 cml microsystems plc d/990/6 april 2008 provisional issue features ? single chip rf transceiver and gmsk modem ? 400mhz - 1ghz radio data systems ? if, rf, control and synthesizer stages ? simple parallel interfacing ? selectable b t = 0.27, 0.3 or 0.5 ? agc algorithm ? receiver sensitivity -116dbm at 8kbps ? rssi measurement ? full mobitex compatibility ? flexible system clocks ? versatile data rates: 4kbps to 16kbps ? suitable for en 300 113, en 300 220 ? packet and freeformat (raw) data and fcc cfr 47 part 90 ? low-power, low profile, low-cost bom 1 brief description a single-chip gmsk packet-data modem and rf transce iver, the cmx990 provides the majority of circuits and functions to implement a full-feature ?wireless modem? subsystem. the cmx990 can operate in rf ranges of 400mhz to 1ghz at data rates of 4 to 16 kbps and is fully mobitex compatible. with a minimum of external components and circuits, th is half-duplex device provides on-chip: a flexible, formattable gmsk packet and free-format modem, a dual synthesiser, if and rf stages for both rx and tx modes, and auxiliary adcs and dacs for system control and monitoring.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 2 d/990/6 this versatile gmsk modem is programmable to both packet and free-format data operations via an efficient task-oriented rx and tx fo rmat and command structure, which is combined with data scrambling, interleaving and fec and crc capabilities. rx data ac quisition, extraction and tracking abilities, allied with rx data quality feedback, allow the cmx990 to operate seamlessly in varying signal environments. tx includes an internal vector modulator to accurate ly generate the modulation. th is is then translated to the final frequency using an offset-phased locked loop. in the rx path an image-reject mixer is provided to minimise external rf filtering requirements. the output of the mixer goes off-chip to allow the circuit designer flexibility in the choice of if filter. t he cmx990 then provides agc functions and i/q mix down to generate baseband signals for the modem. significant rx selectivity is provided using internal i/q baseband filters. comprehensive internal and external system control and monitoring is provided by the 8-bit host interface registers and the on-chip adcs and dacs. requiring a power supply input in the range 3.0 to 3.6 volts, the cmx990 can be used in wireless products designed to comply with such standards as en 300 113 and fcc cfr 47 part 90. operating over a tem perature range of -40c to +85c, the cmx990 consolidates the core radio modem functions to enable a new generation of small, narrow-band wireless data modems. the cmx990 comes in a 64-pin low profile vqfn package.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 3 d/990/6 contents section page 1 brief descr iption .................................................................................................. 1 2 block diag ram ...................................................................................................... 5 3 signal list ............................................................................................................. 6 4 external co mponents.......................................................................................... 9 4.1 layout recomm endations ........................................................................ 9 4.2 processor in terface................................................................................. 10 4.3 synthesiser and tcxo ........................................................................... 11 4.4 transmitte r .............................................................................................. 12 4.5 receiver .................................................................................................. 13 4.6 power supply dec oupling and layout .................................................... 17 5 general descr iption........................................................................................... 19 5.1 baseband m odem................................................................................... 19 5.1.1 description of blocks ................................................................. 19 5.1.2 modem - c in teractio n ............................................................. 21 5.1.3 data form ats ............................................................................. 22 5.1.4 modem inte rface ........................................................................ 23 5.2 rf and if ................................................................................................ 24 5.2.1 transmitter se ction.................................................................... 24 5.2.2 receiver se ction........................................................................ 27 5.3 memory map, interface and register functi ons..................................... 28 5.3.1 data bus buffers ........................................................................ 29 5.3.2 address and r/ w dec ode ......................................................... 29 5.3.3 power-on and reset .................................................................. 29 5.3.4 modem inte rface ........................................................................ 29 5.3.5 power cont rol ............................................................................. 46 5.3.6 auxiliary da c and ad c ............................................................. 47 5.3.7 analogue se tup ......................................................................... 50 5.3.8 special command functi ons..................................................... 51 5.3.9 local oscillator synthesis ers..................................................... 53 5.3.10 clock cont rol ............................................................................. 56 5.3.11 transmitter cont rol bits ............................................................. 57 5.3.12 other transceiver functi ons ..................................................... 58 6 application notes .............................................................................................. 60 6.1 general ................................................................................................... 60 6.2 crc, fec, interleaving and scrambling info rmation: ............................ 60 6.2.1 crc 60 6.2.2 fec 60 6.2.3 interleav ing ................................................................................ 61 6.2.4 scramblin g ................................................................................. 62 6.3 modem application exampl es ................................................................ 63 6.3.1 transmit frame example........................................................... 63 6.3.2 receive frame example............................................................ 65 6.4 transmitte r .............................................................................................. 67 6.4.1 transmitter o-pll frequency tuning range considerations .. 67 6.4.2 start up ...................................................................................... 70 6.4.3 spurious em issions ................................................................... 72 6.4.4 variable bt ................................................................................ 73
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 4 d/990/6 6.4.5 transmitter perf ormanc e ........................................................... 75 6.5 receiver .................................................................................................. 78 6.5.1 architecture overview................................................................ 78 6.5.2 dc calibra tion............................................................................ 83 6.5.3 matching..................................................................................... 84 6.5.4 rx mixer options ....................................................................... 85 6.5.5 signal to noise ........................................................................... 87 6.5.6 dynamic range, r ssi and agc ............................................... 87 6.5.7 signal proc essing ...................................................................... 88 7 performance sp ecificatio n................................................................................ 89 7.1 electrical pe rformanc e............................................................................ 89 7.1.1 absolute maxi mum rati ngs ....................................................... 89 7.1.2 operating limits......................................................................... 89 7.1.3 operating charac teristics .......................................................... 90 7.2 packaging ............................................................................................... 96 it is always recommended that you check for t he latest product datasheet version from the datasheets page of the cml w ebsite: [www.cmlmicro.com].
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 5 d/990/6 2 block diagram figure 1 block diagram
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 6 d/990/6 3 signal list package q1 signal description pin no. name type 1 pa-cntl o/p dac0 output to control pa power. 2 tx fb i/p tx feedback input signal. 3 - nc do not make any connection to this pin 4 v dd tx power power supply to tx if and rf circuits. 5 - nc do not make any connection to this pin 6 v ss tx power return for v dd tx, good decoupling required. 7 txpll o/p tx phase detector output. 8 rf in a i/p rf input a for received signal. 9 rf in b i/p rf input b for received signal. (rf in a and rf in b are a differential input) 10 v dd rx1 power power supply to rx rf circuits. 11 if out o/p output to the external if filter. 12 v ss rx1 power return for v dd rx1, good decoupling required. 13 v ss rx2 power return for v dd rx2, good decoupling required. 14 lna on o/p digital output to turn on external lna block. 15 v dd rx2 power power supply to rx if circuits. 16 if in i/p input from the external if filter. 17 a5 i/p register address select logic inputs. 18 a4 i/p " 19 a3 i/p " 20 a2 i/p " 21 a1 i/p " 22 a0 i/p " 23 v dd dig power power supply to base band digital circuits. 24 v dd ana power power supply to aux adc, dac, op1/2 circuits. 25 v bias o/p output of internal bias generator, decouple to v ss ana. 26 v ss ana power return for v dd ana, good decoupling required. 27 v ss dig power return for v dd dig, good decoupling required. 28 v ss h power return for v dd h, good decoupling required. 29 rdn i/p read. an active low logic level input used to control the reading of data from the modem into the controlling c.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 7 d/990/6 package q1 signal description 30 wrn i/p write. an active low logic level input used to control the writing of data into the modem from the controlling c. 31 csn i/p chip select. an active low logic level input used to enable a data read or write operation. 32 irqn o/p a ?wire-orable? output for connection to the host interrupt request input. this output has a low impedance pull down to v ss when active and is high impedance when inactive. an external pullup resistor is required. 33 v dd h power power supply to host interface and 2.5v regulator circuit. 34 d7 bi tri-state c interface data line. 35 d6 bi " 36 d5 bi " 37 d4 bi " 38 d3 bi " 39 d2 bi " 40 d1 bi " 41 d0 bi " 42 v-cont o/p control signal for external regulating transistor. 43 dac3 o/p aux. d/a 3 output. 44 dac2 o/p aux. d/a 2 output. 45 adc5 i/p aux. a/d 5 input. 46 adc4 i/p aux. a/d 4 input. 47 op2t o/p uncommitted op-amp 2 output, internally connected to adc3. 48 op2n i/p uncommitted op-amp 2 negative input. 49 op2p i/p uncommitted op-amp 2 positive input. 50 op1t o/p uncommitted op-amp 1 output, internally connected to adc2. 51 op1n i/p uncommitted op-amp 1 negative input. 52 op1p i/p uncommitted op-amp 1 positive input. 53 refclk i/p master clock input from external tcxo. 54 tcxo-cntl o/p dac1 output to control tcxo. 55 tcxo-temp i/p a/d input to measure tcxo temperature, internally connected to adc1. 56 loclkn i/p inverted input from the rf oscillator circuit. 57 loclk i/p input from the rf oscillator circuit.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 8 d/990/6 package q1 signal description 58 ifclkn i/p inverting input from if oscillator (if balanced input is used). if ifclk is used as a single ended input this pin should be connected to the vco ground. the pin is a.c. coupled. 59 mainpll o/p main pll output, connect to external filter. 60 v dd vco power power supply to the vco charge pump. 61 auxpll o/p aux pll output, c onnect to external filter. 62 v dd synth power power supply to synthesiser circuits. 63 ifclk i/p input from the if oscillator circuit. 64 pa-temp i/p a/d input to meas ure pa temperature, internally connected to adc0. e xposed m etal p ad sub power the exposed metal pad must be electrically connected to analogue ground (v ss ana). total = 65 pins (64 pins and central metal ground pad) notes: i/p = input o/p = output bi = bidirectional t/s = 3-state output nc = no connection
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 9 d/990/6 4 external components synthesiser op-amp & aux adc interface pa-temp ifclk vdd synth auxpll vdd vco mainpl l ifclkn loclk loclkn tcxo-tem p tcxo-cnt l refclk op1p op1n op1t op2p op2n op2t pa-cntl 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 tx fb 2 47 tx rf nc 3 46 adc4 vdd tx 4 45 adc5 spare aux nc 5 44 dac2 adc & dac vss tx 6 43 dac3 txpll 7 42 v-cont rf in a 8 41 d0 rf in b 9 40 d1 vdd rx1 10 39 d2 if out 11 38 d3 host rx rf vss rx1 12 37 d4 interface vss rx2 13 36 d5 lna on 14 35 d6 vdd rx2 15 34 d7 if in 16 33 vdd h 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 a5 a4 a3 a2 a1 a0 vdd dig vdd ana vbias vss ana vss dig vss h rdn wrn csn irqn host interface host interface cmx990 figure 2 cmx990 pin overview note: in the following sections specified, compone nt tolerances indicate a minimum requirement, components with better tolerances may be substituted. 4.1 layout recommendations to achieve good noise performance, decoupling of v bias and all supplies is very important as is protection of the receive path from extraneous in-band signals. it is recommended that the printed circuit board is laid out with a ground plane in the cmx990 area to provide a low impedance connection between the v ss pins and all v dd and v bias decoupling capacitors. as shown in figure 12 the ground for v ss digital signals should be kept separate from that used for analogue / rf signals. the digital ground should be routed back to a suitable star point.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 10 d/990/6 the cmx990 package has a metal area connected to ground under the main body of the ic. this pad should be connected to analogue ground. it will be noted t hat caution should be exercised over placing any tracks underneath the cmx990. furthermore, any vias other than ground should be avoided under the device unless manufacturers can guarantee t hat the exposed ground pad on the cmx990 will not cause short circuits while a good electrical contact is main tained between the device and ground. apart from these recommendations normal rf layout practices should apply, such as keeping tracks as short as possible, equal track lengths on differential inputs, care with coupling between tracks etc. 4.2 processor interface figure 3 recommended external configuration - processor interface the receiver circuits can be affected by digital noise fr om the host interface. screening of rf circuits is recommended along with filtering of the digital lines. 100 series resistors with 56pf to ground on the cmx990 side of the resistor is suggested however designers are likely to find requirements will vary in individual designs depending on layout, screening arrangements and host. care should be taken to ensure digital control lines a0-a5 are kept away fr om the if input on pin 16 as these address lines are adjacent on pins 17-22.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 11 d/990/6 4.3 synthesiser and tcxo the cmx990 synthesiser section pr ovides two independent synthesisers. the plls implement a type ii loop with a phase / frequency phase detector providi ng an output of a charge pump current. various types of loop filter can be used and should be optimis ed for vco gain of a particular design. figure 4 gives typical configuration and values. cmx 990 auxpll ifclk mainpll balun 1:1 loclk loclkn u1 t2 r80 r87 c100 c99 c101 c116 c114 c113 r91 r79 refclk tcxo-cntl (dac1) c4 c93 c92 ifclkn isolation buffer c102 figure 4 recommended external components ? synthesiser and tcxo c4 1 nf t2 tc1-1-13m+ c92 1 nf c93 1 nf r79 470 c99 100 nf r80 1.0 k c100 27 nf r87 12 k c101 680 nf r91 1.5 k c102 1 nf c113 22 nf c114 1 nf u1 see notes c116 150 nf
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 12 d/990/6 notes: 1 resistors 1%, capacitors 5% unless otherwise stated. 2 for optimum lock time / phase noise it is reco mmended c113 and c116 use a low piezo type such as pps film; optimum performance is not guaranteed with x7r or y5v types. 3 u1 should be a vctcxo or tcxo depending on application requirements. a typical device is the golledge gtxo-83. the cmx990 has a high im pedance input suitable for use with oscillators with clipped sine wave output. an external dc blocking capac itor (as shown, c4) is required. 4 ground currents on the board can result in contamination of the ifclk signal , so for the best possible results use a balun to connect the differential inputs ifclk and ifclkn to the vco. however, adequate elimination of ground noise may be achieved by connection of the ifclkn to the ground of the vco . 5 the ifclk pin needs to be ac coupled. in the case of differential drive it is recommended that external dc- blocking capacitors for both ifclk and ifclkn be used so as to provide equal paths for both complementary signals. 4.4 transmitter the cmx990 transmitter uses an offset phase-locked loop to accurately modulate rf signals. details are contained in subsequent sections of this doc ument. the components used around the cmx990 will depend on application requirements however a typica l configuration is shown in figure 5. figure 5 recommended external components - transmit c86 15 nf r62 18 c89 68 nf r63 270 r64 270 r68 47 r71 36 notes: 1 resistors 1%, capacitors 5% unless otherwise stated. 2 the coupler may be a packaged type (e.g. 0869cp14a090 for 800mhz operation), a lumped element type or printed on the pcb; alternatively a sample of the output can be obtained wi th a resistive or capacitive tap. 3 tx loop filter components need to be optimised for the selected vco.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 13 d/990/6 4.5 receiver the receiver relies on external lna, filtering and t/r switch; details can be found in the following sections. the 1 st mixer in the cmx990 has a differential input. to ensure optimum performance a balun is required when driving from typical single un-balanced lnas or filters. the balun may be a transformer type or implemented using lc networks. the input impedance to the cmx990 mixer is relati vely high so suitable matching components around the balun should be selected for the desired operating frequency to provide a match to the desired impedance e.g. 50 . figure 6 shows a typical configurati on for 800 - 840mhz operation and figure 8 for 360-490mhz operation. two matching configurations can be used for either best noise figure or best inter-modulation performance. in configuration 1 two 100ohm resistors are fitted (r131 and r130). these define the matching impedance but result in a small loss of signal although as the input is essentially a voltage swing the loss is not as much as might be expected. this configuration gives optimum inter-modulation performance. the alternative arrangement is to omit the resistors and match the impedance directly. this results in a small degradation in inter-modulation but provides an improved noise figure. typical results for 800mhz operation are: configuration 1 configuration 2 noise figure (see note 17 section 7.1.3, page 91) 15db 13db input third order intercept point +9.5dbm +6.5dbm 1db compression point -7dbm -9.5dbm r130 r131 l5 c18 c25 t3 l28 input rf in a rf in b cmx990 c18 1 nf l5 8.2 nh c25 1 nf l28 18 nh t3 tc1-1-13m+ r130 100 r131 100 figure 6 recommended external components (800mhz) ? receive mixer configuration 1 notes: 1 resistors 1%, capacitors and inductors 5% unless otherwise stated. 2 values for l5, l28 are typical matching values for 800mhz operation.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 14 d/990/6 c18 c25 t3 input c20 c999 cmx990 rf in a rf in b c18 1 nf c20 4.7 pf c25 1 nf c999 2.2 pf t3 tc1-1-13m+ figure 7 recommended external components (800mhz) ? receive mixer configuration 2 notes: 1 resistors 1%, capacitors and inductors 5% unless otherwise stated. 2 c20, c999 values are typical values for 800mhz operation. r130 r131 l5 c18 c25 t3 l33 input rf in a rf in b cmx990 c18 1 nf l5 56 nh c25 1 nf l33 18 nh r130 100 t3 tc1-1-13m+ r131 100 figure 8 recommended external components (400mhz) ? receive mixer configuration 1
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 15 d/990/6 ch1 s 22 log mag 10 db/ ref 0 db start 200.000 000 mhz stop 600.000 000 mhz cor del prm marker 3 400 mhz 1 2 3 4 5 3_:-17.238 db 400.000 000 mhz 1_:-2.9831 db 200 mhz 2_:-5.5423 db 300 mhz 4_:-8.4907 db 500 mhz 5_:-3.1645 db 600 mhz figure 9 400mhz input match return loss with matching as figure 8. the output of the cmx990 first receive mixer should be at an if in the range 44 to 46mhz. only if?s in this range will benefit from the image reject functionalit y of the mixer. between the mixer and if amplifier stages a crystal filter is recommended. this filter is to protect the if amplifier and subsequent stages from off-channel signals. matching arrangements will va ry, being dependant on the filt er used, however an example of a typical configuration fo r a 45mhz if is given in figure 10.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 16 d/990/6 cmx990 l4 f1a / f1b c50 c51 c46 l2 c48 r36 c41 ifout ifin c41 1 nf l2 1.2 h c46 1 pf l4 1.2 h c48 1 pf r36 680 c50 4.7 pf f1 ma08340 c51 5.6 pf figure 10 recommended external components ? receive if section notes: 1 resistors 1%, capacitors and inductors 5% or better unless otherwise stated. 2 f1 is a smt 4 pole crystal filter implemented as a matched pair with a 6khz pass-band, load 500r//4pf, cc = 13pf. the part is available from golledge electronics ( www.goll edge.com). other parts may be equally suitable although matching arrangements will vary and diffe rent filters are recomm ended for different channel bandwidths and performance requirements. when select ing and matching a crystal filter care should be taken to ensure a flat pass-band and the performance should always be checked with a specific pcb layout. for further information on filter sele ction see section 6.5.1 and table 3.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 17 d/990/6 4.6 power supply decoupling and layout the cmx990 has dual supply voltages: a 3.3v supply is required for the plls and charge pump circuits and for the digital i/o pads, and a 2.5v supply (with s eparate decoupling) is required for the rf sections (rx1, rx2, tx) as well as the baseband analogue and digital circuits. the 3.3v supply must be provided by an external regul ator circuit. the 2.5v supply may be provided by an external regulator, or alternatively may be derived fr om the 3.3v supply using an off-chip low saturation voltage transistor in conjunction with the on-chip cont rol circuit (enabled by register powerup1 bit 5) - an example of this arrangement is shown in figure 11. whichever method is used to generate the 2.5v it is essential that all the circuits relying on this supply are powered down before this 2.5v source is turned off. the cmx990 will then allow the supply to drop to 2.0v, at which point it will be clamped by a separate on- chip micropower regulator. this is done so that the dat a in the on-chip registers and memories is not lost. the main 2.5v regulator circuit must be power ed up again and allowed to settle before any rf or analogue circuitry, or the clock to the internal logic, is enabled. in other words, powerup1 ($04 - bits 7-6 and 4-0) and powerup2 ($05 - bits 7-4 and 0) must be set low whenever the 2.5v supply is unavailable. the circuit shown in figure 11 is an example, and will r equire that the 3.3v supply is regulated to within +/- 5%. this is necessary to ensure that the pnp transistor shown (tr3) does not enter saturation, taking worst case ambient conditions and bandgap / component tolerances into account. v dd ana (24) bandgap cmx990 reference (33) v dd h 3.3v supply low power - 2v reg + r126 (23) v dd dig tr3 high power 2.5v reg r125 2.5v supply - control circuit (42) vcont + (pin number) c158 enable figure 11 voltage regulator connections c158 100 f r125 330 tr3 pmbt4403 r126 47 k resistors 5%, capacitors 20% or better.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 18 d/990/6 r7 v dd h 3.3v r6 v dd vco r5 v dd dig r4 v dd synth 2.5v r3 v dd plane for rx2 & ana r2 v dd plane for rx1 r1 v dd plane for tx c7 c6 c5 c4 c3 c2 c1 gnd plane for: v ss rx1 gnd v ss rx2 gnd for: v ss dig v ss synth v ss hv ss ana figure 12 power supply connections and de-coupling c1 10 nf r1 2.2 c2 10 nf r2 2.2 c3 10 nf r3 3.3 c4 10 nf r4 10 c5 10 nf r5 10 c6 10 nf r6 10 c7 10 nf r7 10 resistors 5%, capacitors 20% unless otherwise stated. note: it is expected that low frequency interference on the 3.3 volt supply will be removed by active regulation; although a large capacitor is an alternative it may require more board space and so may not be preferred by the user. it is particularly im portant, however, to ensure that t here is no interference from the v dd h (which supplies the digital i/o) or from any other circuit that may use the 3.3v supply (such as a microprocessor) to sensitive analogue supplies like v dd vco or, importantly, the external rf vco supplies. the supply decoupling shown is intended for rf noise s uppression only. it is necessary to have a small series impedance prior to the decoupling capacitor for the decoupling to work efficiently with physically small capacitors; this may be cost effectively done with the resistor and capacitor values shown. the use of resistors results in a small dc voltage drops ( up to approx 0.1v). choosing resistor values approximately inversely proportional to the dc curr ent requirements of each supply, ensures the dc voltage drop on each supply are reasonably matc hed. the internal regulator uses v dd ana as its feedback, so this will compensate to reduce this vo ltage drop. in any case the dc voltage change that results is well within the design tolerance of t he device. if higher impedance resistors are used (not recommended) then greater care will be needed to ensur e the supply voltages are maintained within tolerance, even when individual parts of the device are enabled or disabled.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 19 d/990/6 5 general description the cmx990 comprises a baseband modem and an asso ciated rf section to provide a gmsk data modem including the ability to support the mobitex air-i nterface. device control and status is transferred via a set of memory mapped registers. an overview of the operation of the modem is provided in section 5.1 and the rf / if functions in section 5.2. these are followed by detailed description of the host c interface in section 5.3. further applicati on information is contained in section 6. 5.1 baseband modem this section has been designed to be compliant with t he appropriate sections of the "mobitex interface specification" including short block frame form atting for the extended battery saving protocol. references to ?data blocks? in this section apply to both the normal (18 byte) data block and the smaller (4 byte) short data block. the function of this section is further divided into receive and transmit sections that operate in half duplex. in transmit mode the data may be encoded according to the mobitex standard. this includes the calculation and appending of a cyclic redundancy c hecksum (crc) and forward error correction (fec), and interleaving to reduce the effects of noise (note these functions can be bypassed if required). the subsequent nrz data stream is then filtered digitally and the resu lting digital data processed to produce an i and q signal as the baseband form of the required fm signal. these are converted to analogue signals via d-a converters and passed to the rf section for subsequent transmission. in receive mode, the analogue i and q representations , at baseband, of the fm signal from the rf section are converted to digital signals via a-d conver ters. these signals are digitally filtered to suppress the adjacent channels and demodulated digitally. the resu lting signal is then filtered, to optimise the signal to noise performance, before slicing to resolve into a digital bit stream. mobitex specified error correction and de-interleaving can be applied and the resulting data is presented for transfer to an external processor. 5.1.1 description of blocks status and data quality registers 8-bit registers which the c can read to determine t he status of the modem and the received data quality. command, mode and control registers the values written by the c to these 8-bi t registers control the operation of the modem. data buffer an 18-byte buffer used to hold receive or transmit data to or from the c.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 20 d/990/6 frame assembly / disassembly each of these blocks consists of 4 circuits which generate (in transmit mode) or check (in receive mode) the bits of both short and normal mobitex data blocks. crc generator/checker a circuit which generates (in transmit) or che cks (in receive) the crc bits, which are included in transmitted mobitex data blocks so that the receive modem can detect transmission errors. fec generator/checker in transmit mode this circuit calculates and adds the fec (4 bits) to each byte presented to it. in receive mode the fec information is used to correct most transmission errors that have occurred in mobitex data blocks or in the frame head control bytes. interleave/de-interleave buffer this circuit interleaves data bits within a data block before transmission and de-interleaves the received data block so that the fec system is best able to handle short noise bursts or signal fades. scramble/de-scramble this block may be optionally used to scram ble/de-scramble the transmitted and received data blocks. it does this by modulating the data with a 511-bit pseudorandom sequence, as described in section 6.2.4. scrambling impr oves the transmitted spectrum, especially when repetitive sequences are to be transmitted. frame sync detect this circuit, which is only active in receive mode, is used to look for the user specified 16-bit frame synchronisation pattern which is transmitt ed to mark the start of every frame. tx modulator and low pass filter the filter is used in transmit mode and is a low pass tr ansitional gaussian filter having a 3db loss at 0.27, 0.3 or 0.5 times the bit rate (bt=0. 27, 0.3 or 0.5). see figure 13. th is filter eliminates the high frequency components which would otherwise cause interference into adjacent radio channels. the bt=0.27 option is added as means of meeting the more stringent regulatory requirements for adjacent channel power (for example en 300 113). the unmodulated baseband ?eye? diagrams of the tr ansmitted signal is shown in figure 14. the tx modulator converts the baseband signal into an i and q form which is passed to the tx if stage. figure 13 typical tx baseband filter response
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 21 d/990/6 figure 14 baseband transmitter signal eye diagrams rx low pass filter this filter is a low pass transitional gaussian filter having a 3db loss at 0.56 times the bit rate (bt=0.56). it is used to reject hf noise to improve the ber. level track and dpll these circuits, which operate only in receive mode, extract a bit rate clock from the received signal and measure the received signal amplitude and dc offset. this information is then used to extract the received bits and also to provide an input to the received data quality measuring circuit. 5.1.2 modem - c interaction in general, data is transmitted over air in the form of messages, or ?frames?, consisting of a ?frame head? optionally followed by one or more formatted data blocks. the frame head includes a frame synchronisation pattern designed to allow the receivi ng modem to identify the start of a frame. the following data blocks are constructed from the ?raw ? data using a combination of crc (cyclic redundancy checksum) generation, forward error correction codi ng, interleaving and scrambling. details of the message formats handled by this modem are given in se ction 5.1.3 and further information is given in sections 6.2, 6.2. 3, 6.2.4 and 6.3. to reduce the processing load on the host c, this modem has been designed to perform as much as possible of the computationally intensive work involved in frame formatting and de-formatting and (when in receive mode) in searching for and synchronisi ng onto the frame head. in normal operation the modem will only require servicing by the c once per received or transmitted data block. thus, to transmit a block, the host c has only to load the unformatted (raw) binary data into the modem's data buffer then instruct the modem to format and tr ansmit that data. the modem will then calculate and add the crc bits as required, encode the result with forward error correction coding, interleave then scramble the bits before transmission. in receive mode, the modem can be instructed to asse mble a block?s worth of received bits, de-scramble and de-interleave the bits, check and correct them (using the fec coding) and check the resulting crc before placing the received binary data into the data buffer for the c to read. the modem can also handle the transmission and rec eption of unformatted data, to allow the transmission of special bit and frame synchronisation sequences, test patterns or custom data formats.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 22 d/990/6 5.1.3 data formats raw data if required the user may transmit and receive raw data. this is transferred between the host and device a byte (8 bits) at a time. note that it is important to have established fr ame synchronisation before receiving data to enable the receiving device to decode synchronously. the user may add error detection and correction by way of algorithms performed on the host device. general purpose formats in a proprietary system the user may employ the data elements provided by this device to construct a custom, over-air data structure. for example, 16 bits of bit sync + 2 bytes of frame sync + 4 bytes of receiver and sender address + n data blocks would be sent as: tqb (bit and frame sync) + tqb (addresses) + (n x tdb) + tsb and received as: sfs + rsb + rsb + rsb + rsb + (n x rdb) mobitex frame structure the mobitex format for transmitted data is in the form of a frame head immediately followed by either 1 short data block or a number of data blocks (0 to 32). the frame head consists of 7 bytes: 2 bytes of bit sync: 1100110011001100 from base, 0011001100110011 from mobile bits are transmitted from left to right 2 bytes of frame sync: system specific. 2 bytes of control data. 1 byte of fec code, 4 bits for each of the control bytes: bits 7-4 (leftmost) operat e on the first control byte. bits 3-0 (rightmost) operate on the second control byte. each byte in the frame head is transmitt ed bit 7 (msb) first to bit 0 (lsb) last. the normal and short data blocks consist of: 18 bytes of data (data block) or 4 bytes of data (short data block). 2 bytes of crc calculated from the data bytes. 4 bits of fec code for each of the data and crc bytes the resulting data block bits are in terleaved and scrambled before transmission. figure 15 shows how the over air signal is built up fr om frame sync and bit sync patterns, control bytes and data blocks. the binary data transferred between the modem and the host c is that shown enclosed by the thick dashed rectangl es near the top of the diagram.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 23 d/990/6 figure 15 mobitex over air signal format 5.1.4 modem interface the data modem interfaces to the rf circuits using i and q format for both transmit and receiver. operation can be seen in figure 1. on the transmi tter the frame assembly block feeds data to the modulator which creates i and q data streams for in ternal digital to analogue converters (dac). the
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 24 d/990/6 output of the dac is differential and is filtered to remove spurious responses before being passed to the analogue rf stages. the input to the receiver section of the modem comes from the analogue receiver stages as a differential signal in i/q format. anti-alias filters are used prior to analogue to digital conversion (adc). the analogue circuits include the ability to minimise dc offset e rrors, thus optimising the dynamic range of the signal. further dc offset correction is applied in the signal processing after the adc (for further details see section 6.5.2). following the adc fi r channel filters (see section 6.5.1) are applied prior to demodulation and associated timing recovery and synchronisation. 5.2 rf and if the cmx990 is a broadband rf modem system. the rf section can support transmission and reception between 400mhz and 1ghz. the transmitter and receiver parts are designed for half duplex operation so should be operated mutually exclusively - normally the non-utilised part being pow ered down when not in use. for single antenna operation an external transmit/recei ve (t/r) switch is required. the transmitter takes the baseband i and q signals from the modem (see section 5.1 and figure 1) and up-converts them via a quadrature modulator to a suit able intermediate frequency (if). an offset pll is then used to control an external vco which translate s the if to the desired transmission frequency. the output of the vco is sampled, usually after amplif ication, and mixed down to the if; this mixed down signal is then phase/frequency compared with the if si gnal from the quadrature modulator. the output of the phase comparator is fed to an external loop filter , which controls the vco thereby closing the loop. the vco output then will be an fm signal at the r equired rf frequency having a low out-of-band spurious response typical of vco driven trans mitters whilst guaranteeing a modulati on index of exactly 0.5. the output of the vco requires amplifying wi th an external pa (power amplifier). the receiver requires use of an external lna with some pre-filtering and an external balun. the differential output from the balun is down converted by an image reject mixe r to a suitable if (typically 45 mhz). the single ended if signal is filtered with an ex ternal filter to remove spurious signals and this goes into an agc stage with a gain control range of 45db . the output of the agc is mixed down to i and q signals at baseband via quadrature mixers. the i and q signals are amplified and filtered to remove any signals that may alias with the subsequent a-d samp ling. the amplifier also has a coarse offset removal system to allow the approximate nulling of dc offsets developed in the circuits that may restrict the dynamic range in the subsequent processing. as with any rf system care is required with frequency planning to minimise component count, avoid spurious responses etc. a examples of typi cal frequency planning is shown in figure 17 and further discussion is given in section 6.5.1. 5.2.1 transmitter section i and q signals from the modem block are base-band representations of the required modulated rf signal. these are up-converted by a quadrature modul ator stage to a suitable if. the summed output from this stage has the required modulation index but at a lower frequency (txif, typically 45mhz or 90mhz) than that required for transmi ssion. the cmx990 provides either divide by 2 or divide by 4 from the programmed auxiliary local oscillator frequency to aid if selection. an offset phase locked loop (o-pll) is used to trans late this modulated txif signal to the appropriate carrier frequency. the o-pll architecture is show n in figure 16. the o-pll works as a feedback loop with the txif signal as it?s reference input. consi dering the forward path the final frequency modulation is generated by a vco which then drives a power amplif ier to generate the required output level. the full power signal is sampled and then attenuated externa lly and / or on chip. for the signal sampling a directional coupler is recommended although a simp le sample of the pa output can be used. the
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 25 d/990/6 attenuated signal is then down-mixed with the main lo signal to a frequency nominally the same as the txif value. the resulting signal is low-pass filter ed to remove unwanted mixer products. this filter can be set to two values depending on the txif in use (sec tion 5.3.11). a high gain limiting amplifier is then used to enable the loop to have a high dynamic range and to lock-in even when the transmitted signal is very small, e.g. when just starting to ramp up. the output of the limiting amplifier is then phase/frequency compared with the txif reference signal from the modulator, the charge pump output being passed off chip into a suitable loop filter. the filtered output controls the vco with its nominal frequency set to the middle of the required transmission band. when the loop is locked, the vco follows the frequency modulations of the reference signal so as to give an exact modulation index of 0.5 whilst having the low spurii in transmission typical of a vco based system. phase detector + 90 i q if lo txif filter limiter main lo vco loop filter figure 16 block diagram of offset phase locked loop transmitter as noted above, the output of the vco is generally amplified with a power amplifier. a special feature of one of the auxiliary d-a converters may be used to c ontrol the ramping of the power amplifier optimally should this be required. this feature is explained in section 5.3.6. the auxiliary a-d section can also be used for sensing the forward and reverse power val ues, and the pa temperature should these features be required. further information on the transmitter operation can be found in section 6.4.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 26 d/990/6 figure 17 simplified block diagram of cmx990 showing example frequency plan for 864-870mhz (rx) / 819-825mhz (tx) band
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 27 d/990/6 5.2.2 receiver section it is expected that the signal from the t/r switch will be amplified via an external lna. the use and positioning of an image reject filtering is up to the r adio designer. as a guide, the mobitex specification requires a minimum of 45db of first image rejection of which at least 30db will be provided by the on-chip image reject mixer stage. the design is optimised with an lna gain of about 15db. it has been assumed that there is some insertion loss prior to the ln a; but an overall noise figure of 4db and gain of 10db (approx.) is achieved by the circuits preceding the cmx990. a digital c ontrol signal is available from the chip which should be used to enable/disable the lna. a balun must be used to produce a differential signal to the first mixer on the chip. the image reject mixer down-converts the signal to 45 mhz, although this frequency may be changed slightly if necessary, for example when used in regi ons where there may be conf licts with local broadcast transmissions. the resulting if is then output from the chip as a single ended signal for filtering. a relatively low cost crystal filter can be used to remove signals outside the channel bandwidth. the specification of this filter will vary with the intent ed application. for detailed filt er requirements see table 3 (section 6.5.1). the if-signal from the filter is then taken back on ch ip to an amplifier stage which includes gain control, thus allowing automatic gain control (agc) to be im plemented. the agc is adjustable in steps of 15db from -5db to +40db and can be adjusted automatically by the chip or may be controlled by instruction from the host processor. the output from the agc is then mixed down to baseband, by a quadrature mixer stage, to produce i and q signals. these are then filtered, to remove unwanted mixer products, spurii and remaining blocking signals and at the same time amplified to a suitable le vel for subsequent a-d conversion. the filters also precondition the signal to prevent aliasing with the a-d sample frequency. channel filtering is provided digitally in the baseband processing section (see section 6.5.1).
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 28 d/990/6 5.3 memory map, interface and register functions the following is a summary of the internal register s as seen by the host, details of operation may be found in the relevant section. address read write $00 data buffer (rx) data buffer (tx) $01 status 1 command $02 data quality control $03 status 2 mode $04 freq offset power up 1 $05 rssi power up 2 $08 aux adc 0 lsb aux dac 0 lsb $09 aux adc 0 msb aux dac 0 msb $0a aux adc 1 lsb aux dac 1 lsb $0b aux adc 1 msb aux dac 1 msb $0c aux adc 2 lsb aux dac 2 lsb $0d aux adc 2 msb aux dac 2 msb $0e aux adc 3 lsb aux dac 3 lsb $0f aux adc 3 msb aux dac 3 msb $10 aux adc 4 lsb ram dac control $11 aux adc 4 msb aux adc control 1 $12 aux adc 5 lsb aux adc control 2 $13 aux adc 5 msb - $14 - aux ram data1 lsb $15 - aux ram data1 msb $16 - aux ram data2 lsb $17 - aux ram data2 msb $18 analogue setup 1 analogue setup 1 $19 analogue setup 2 analogue setup 2 $1a - special command $1b special data0 lsb special data0 lsb $1c special data0 msb special data0 msb $1d special data1 lsb special data1 lsb $1e special data1 msb special data1 msb $20 - main pll m div lsb $21 - main pll m div msb $22 - main pll n div lsb $23 - main pll n div nsb $24 - main pll n div msb $25 - aux pll m div lsb $26 - aux pll m div msb $27 - aux pll n div lsb $28 - aux pll n div msb $29 - clock control $3f - test output (see section 5.3.8.4) note: all unused addresses from $00 to $3f are reserved for future use.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 29 d/990/6 5.3.1 data bus buffers the circuitry driving the d0-7 pins consists of 8 in ternal bidirectional 3-state logic level buffers between the internal registers and the external data bus lines. 5.3.2 address and r/w decode transfer of data bytes between the c and the internal r egisters is controlled accord ing to the state of the write and read enable inputs (wrn and rdn), the chip select input (csn) and the register address inputs a0 to a5. the data bus buffers, address and r/w decode blocks pr ovide a byte-wide parallel c interface, which can be memory-mapped, as shown in figure 3. 5.3.3 power-on and reset when the power is first applied to the device an internal circuit will reset internal registers to a known state and put all circuit blocks in an inactive and pow er saved state with the exception of the 'enable clock bit' in 'power up 1' register (section 5.3.5). this bit is set to '1' so that the device may respond to the tcxo clock which the reset task needs to complete its cycle. the small current that this clock enable circuit uses ma y be saved by writing all ?0?s to the 'power up 1' register through the micro interface. read bits will be rese t to '0' - the inactive state. counters / states will be reset to an inactive and known condition after a reset event - which can occur asynchronously. setting the reset bit (register $05, see section 5.3.5) to '1' is similar except the reset bit does not control the 'v reg?, 'preserve regist ers' and 'vbias' bits (shown in bold in the following register diagrams) and the ?clock control register? ($29, see section 5.3.10) , they will remain at the last programmed state. if minimum power is required and the ?clock control regi ster? is using a value other than its default value of $18, it must be re-programmed with $18. 5.3.4 modem interface the modem appears to the programmer as a series of 8-bit read and write registers, individual registers being selected by the a0 to a5 address pins. most of the baseband control for formatting or decoding the data is controlled by the following registers: address write to modem read from modem $00 data buffer data buffer $01 command register status 1 register $02 control register data quality register $03 mode register status 2 register 5.3.4.1 data buffer data buffer $00 write bit: 7 6 5 4 3 2 1 0 tx data data buffer $00 read bit: 7 6 5 4 3 2 1 0 rx data
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 30 d/990/6 this is an 18-byte read/write buffer which is used to transfer data (as opposed to command, status, mode, data quality and control information) between the modem and the host c. it appears to the c as a single 8-bit register; the m odem ensuring that sequential c reads or writes to the buffer are routed to the correct locations within the buffer. the c should only access this buffer 2 s after the stat us register bfree (buffer free) bit is set to ?1?. the buffer should only be written to while in tx mode and read from while in rx mode (except when loading frame sync detection bytes while in rx mode). 5.3.4.2 command register writing to this register tells the modem to perform a specific action or actions, depending on the setting of the task and acquire bits. the enable packet detect bit is used to indicate the presence of data signals in the receive path. command register $01 write bit: 7 6 5 4 3 2 1 0 acquire bit clock acquire i q offset acquire afc enable packet detect task control when it has no action to perform (but is not ?powersa ved?), the modem will be in an ?idle? state. if the modem is in transmit mode the input to the tx filter will be connected to a mid level. in receive mode the modem will continue to measure the received data quality and extract bits from the received signal, supplying them to the de-interleave buffer, but will otherwise ignore the received data. command register b7: acquire bit clock this bit has no effect in transmit mode. in receive mode, whenever a byte with the acquire bit clock set to ?1? is written to the command register, and task is not set to reset, it initiates an automatic sequence designed to achieve bit timing synchronisation with the received signal as quickly as possible. this involves setting the phase locked loop of the received bit timing extraction circuits to its widest bandwidth, then gradually reducing the bandwidth as timing synchronisation is achieved, until it reaches the 'normal' value set by the pll control bits of the control register. setting this bit to ?0? (or changing it from ?1? to ?0?) has no effect, however note that the acquisition sequence will be re-started every time that a byte wr itten to the command register has the acquire bit clock bit set to ?1?. details of the acquisition sequence are in section 5.3.4.3. the acquire bit clock will normally be set to '1' up to 12 bits before an sfs (search for frame sync) or sfh (search for frame head) task, however it may also be used independently to re-establish clock synchronisation quickly after a long fade. alternat ively, a sfs or sfh task may be written to the command register with the acquire bit clock bit set to ?0? if it is known that clock synchronisation does not need to be re-established. details of t he acquisition sequence are in section 5.3.4.3. command register b6: acquire i q offset this bit has no effect in transmit mode. in receive mode, when this bit is changed from a '0' to a '1' it initiates an automatic sequence designed to compensate the dc offset of the received i and q signal . this sequence involves temporarily disabling the rf input and measuring dc offset and applying an appropriate correction. once this has been completed the rf input will be reasserted and operation will then depending on the setting of bits 4 and 5 of the control register ($02). details of the ac quisition sequence are in section 5.3.4.3.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 31 d/990/6 changing this bit from ?1? to ?0? will terminate acquisition and the ?normal? value set by bits 4 and 5 of the control register ($02) will be carried out. the acquire i q offset bit will normally be set afte r changing or reacquiring a channel (e.g. after powering up from a sleep condition). this would normally be done so the acquisition sequence was completed before an sfs or sfh task is initiated. alternativ ely, a sfs or sfh task may be written to the command register without previously setting the acquire i q offset bit to ?1? if it is known that there is no need to re- establish the received signal offsets, e.g. when receiving another message on the same channel in quick succession. note: sfh or sfs task should be set when the acquire i q offset has completed and 12 bits after setting the acquire bit clock sequence. for further discussi on on i/q offset correction see section 6.5.2. command register b5: acquire afc this bit has no effect in transmit mode. in receive mode, when this bit is changed from a '0' to a '1' it initiates an automatic sequence designed to measure and compensate for small differences in the carrier frequencies of the transmitter and receiver. if the tcxo frequency is too far out the dc offset in the demodulated signal will become excessive and limit the decode performance of the device. in thes e cases the host must adjust the tcxo frequency via the on chip dac based on the value read fr om the frequency offset register ($04). in mobitex systems the carrier frequencies of basesta tions are very accurate compared to the permitted tolerances of mobile units. therefore once a mobile unit has set up it's local tcxo frequency it should be suitable for transmitting or receiving with any basesta tion. the slow tracking mode should be sufficient to track any variations caused by environmental changes. details of the acquisition sequence are in section 5.3.4.3. command register b4: enable packet detect this bit has no effect in transmit mode. in receive mode if this bit is set to '1' the devic e will monitor the demodulated waveform for signals likely to be valid data. the likely presence of valid data will be reported via bit 0 of status register 1. this information can assist in the timing of setting a sf s or sfh task. note that some noise signals may appear in the baseband as valid data, the rssi signal should be used to confirm that the received signal is suitable before relying on this signal, bearing in mind the rssi averaging time, see section 5.3.8.6. it is recommended that this bit is only set to ?1? when searching for the start of a packet. once a frame sync has been detected this bit should be set to ?0 ? until the start of a new packet needs to be found. command register b3, b2, b1, b0: task operations such as transmitting a data block are tr eated by the modem as ?tasks? and are initiated when the c writes a byte to the command register with the task bits set to one of the data handling commands (marked bold in the table below). mobitex modem tasks: b3 b2 b1 b0 receive mode transmit mode 0 0 0 0 null null 0 0 0 1 sfh search for frame head t7h transmit 7 byte frame head 0 0 1 0 r3h read 3 byte frame head reserved 0 0 1 1 rdb read data block tdb transmit data block 0 1 0 0 sfs search for frame sync tqb transmit 4 bytes 0 1 0 1 rsb read single byte tsb transmit single byte 0 1 1 0 lfsb load frame sync bytes tso transmit scrambler output 0 1 1 1 reset cancel any current action reset cancel any current action 1 0 0 1 sfhz sfh with zero errors reserved 1 0 1 1 rsd read short data block tsd transmit short data block 1 1 0 0 sfsz sfs with zero errors reserved
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 32 d/990/6 note: all other bit patterns are reserved. bold text indicates a ?data handling command? the c should not write a data handling command to the command register or write to or read from the data buffer when the bfree (buffer free) bi t of the status 1 register is ?0?. different tasks apply in receive and transmit modes. detailed timings for the various tasks are given in figure 20 and figure 21. 5.3.4.2.1 transmit operation when the modem is in transmit mode, all data handli ng commands other than tso instruct the modem to transmit data from the data buffer, formatting it as required. for these tasks the c should wait until the bfree (buffer free) bit of the status 1 register is ?1 ?, before writing the data to the data buffer. if more than 1 byte needs to be written to the data buffer, by te number 0 of the block should be written first. the host should then write the desired task to the command register. once the byte containing the desired task has been wr itten to the command register, the modem will: set the bfree (buffer free) bit of the status 1 register to ?0?. take the data from the data buffer as quickly as it can - transferring it to the interleave buffer for eventual transmission. this operation will start immediately if the modem is ?idle? (i.e. not transmitting data from a previous task), otherwise it will be delayed until there is sufficient room in the interleave buffer. once all of the data has been transferred from the data buffer the modem will set the bfree and irq bits of the status 1 register to ?1?, (causi ng the chip irqn output to go low if the irq enable bit of the mode register has been set to ?1?) to tell the c that it may write new data and the next task to the modem. in this way the c can write a task and the asso ciated data to the modem while the modem is still transmitting the data from the previous task. see figure 18. figure 18 the transmit process
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 33 d/990/6 5.3.4.2.2 receive operation when the modem is in receive mode, the c should wait until the bfree bit of the status 1 register is ?1?, then write the desired task to the command register. once the byte containing the desired task has been wr itten to the command register, the modem will: set the bfree bit of the status register to ?0?. wait until enough received bits are in the de-interleave buffer. decode them as needed, and transfer any resulting data to the data buffer. then the modem will set the bfree and irq bits of status 1 register to ?1?, (causing the irqn output to go low if the irq enable bit of the mode regi ster has been set to ?1?) to tell the c that it may read from the data buffer and write the next task to the modem. if more than 1 byte is contained in the data buffer, byte number ?0? of the data will be read first. in this way the c can read data and write a new task to the modem while the received bits needed for this new task are being stored in the de-interleave buffer. see figure 19. the above is not true for loading the frame sync detec tion bytes (lfsb): the bytes to be compared with the incoming data must be loaded prior to the task bits being written. figure 19 the receive process task descriptions: null - no effect this task is provided so the acquisition commands can be issued without loading a new task. sfh - search for frame head causes the modem to search the received signal fo r a frame head. the frame head will consist of a 16-bit frame sync followed by control data (see figure 15- mobitex over air signal). the search will continue until a frame head has been found, or until the reset task is loaded. the search is carried out by first attempting to match the incoming bits against the previously programmed (task lfsb) 16-bit frame sync pattern (allowing up to any one bit (of 16) in error). when a match has been found, the modem will read the next 3 re ceived bytes as frame h ead bytes, these bytes will be checked, and corrected if necessary, using t he fec bits. the two frame head data bytes are then placed into the data buffer. the bfree and irq bits of the status 1 register will t hen be set to a logic ?1? to indicate that the c may read the 2 frame head data bytes from the da ta buffer and write the next task to the command
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 34 d/990/6 register. if the fec indicates uncorrectable errors the modem will set the crcfec bit in the status 1 register to a logic ?1?. the moban bit (mobile or ba se) in the status 1 register will be set according to the polarity of the 3 bits preceding the frame sync pattern. r3h - read 3-byte frame head this task, which would normally follow an sfs task, w ill place the next 3 bytes directly into the data buffer. it also causes the modem to check the 3 bytes as frame head control data bytes and will set the crcfec bit to a logic ?1? (high) only if the fec bits indicate uncorrectable errors. note: this task will not correct any errors and, due to the mobitex fec specification, will not detect all possible uncorrectable error patterns. the bfree and irq bits of the stat us 1 register will be set to ?1? when the task is complete to indicate that the c may read the dat a from the data buffer and write the next task to the modem's command register. the crcfec bit in the status 1 register will be set according to the validity of the received fec bits. rdb - read data block this task causes the modem to read the next 240 bits as a mobitex data block. it will de-scramble and de-interleave the bits, fec co rrect and crc check the resulting 18 data bytes and place them into the data buffer, setting the bfree and irq bits of the status 1 register to ?1? when the task is complete to indicate that the c may read the data from the data buffer and write the next task to the modem?s command register. the crcfec bit w ill be set according to the outcome of the crc check. note: in receive mode the crc checksum circuits ar e initialised on completion of any task other than null. sfs - search for frame sync this task, which is intended for special test and c hannel monitoring purposes, performs the first part only of a sfh task. it causes the modem to search the received signal for a 16-bit sequence which matches the frame synchronisation pattern with up to any 1 bit in error. when a match is found the modem will set the bfree and irq bits of the status 1 register to ?1? and update the moban bit. the c may then write the next task to the command register. rsb - read single byte this task causes the modem to read the next 8 bits and translate them directly (without de-interleaving or fec) to a single byte which is placed into the data buffer (b7 will represent the earliest bit received). the bfree and irq bits of the status 1 register will then be set to ?1? to indicate that the c may read the data byte from the data buffer and writ e the next task to the command register. this task is intended for special tests and channel monitoring - perhaps preceded by an sfs task. lfsb - load frame sync bytes this task takes 2 bytes from the data buffer and updates the frame sync detect bytes. the msb of byte ?0? is compared to the first bit of a received frame sync pattern and the lsb of byte ?1? is compared to the last bit of a received frame sync pattern. this task does not enable frame sync detection. unlike other rx tasks, the data buffer must be loaded bef ore the task is issued. this task must only be issued after a minimum of 4 bit times after a command register reset task. as mobitex frame sync detect bytes are usually nationally or regionally se t, this operation may easily be done after power up, or when changing channels. once the modem has read the frame sync bytes from the data buffer, the bfree and irq bits of the status 1 register will be set to ?1?, indicating to the c that it may write the next task to the modem.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 35 d/990/6 sfhz - search for frame head with zero errors this performs the same task as sfh task but allowing no bits to be in error over the 16-bit frame sync pattern. rsd - read short data block this task causes the modem to read the next 72 bits as a mobitex short data block. it will de-scramble and de-interleave the bits, fec co rrect and crc check the resulting 4 data bytes and place them into the data buffer, setting the bfree and irq bits of the status 1 register to ?1? when the task is complete to indicate that the c may read the data from the data buffer and write the next task to the modem?s command register. the crcfec bit w ill be set according to the outcome of the crc check. note: in receive mode the crc checksum circuits ar e initialised on completion of any task other than null. sfsz - search for frame sync with zero errors this performs the same task as sfs task but allowing no bits to be in error over the 16-bit frame sync pattern. t7h - transmit 7-byte frame head this task takes 6 bytes of data from the data buffer, calculates and appends 8 bits of fec from bytes ?4? and ?5? then transmits the result as a complete mobitex frame head. bytes ?0? and ?1? form the bit sync pattern, bytes ?2 ? and ?3? form the frame sync pattern and bytes ?4? and ?5? are the frame head control bytes. bit 7 of byte ?0? of the data buffer is sent first, bit 0 of the fec byte last. once the modem has read the data bytes from the data buffer, the bfree and irq bits of the status 1 register will be set to ?1?, indicating to the c t hat it may write the next task and its data to the modem. tqb - transmit 4 bytes this task takes 4 bytes of data from the data buffer and transmits them, bit 7 first. once the modem has read the data bytes from the data buffer, the bfree and irq bits of the status 1 register will be set to ?1?, indicating to the c t hat it may write the next task and its data to the modem. tdb - transmit data block this task takes 18 bytes of data from the data bu ffer, calculates and applies a 16-bit crc and forms the fec for the 18 data bytes and the crc. this data is then interleaved and passed through the scrambler, if enabled, before being transmitted as a mobitex data block. once the modem has read the data bytes from the da ta buffer, the bfree and irq bits of the status register will be set to ?1?, indicating to the c t hat it may write the next task and its data to the modem. note: in transmit mode the crc checksum circuit is in itialised on completion of any task other than null. tsb - transmit single byte this task takes a byte from the data bu ffer and transmits the 8 bits, bit 7 first. once the modem has read the data byte from the data buffer, the bfree and irq bits of the status 1 register will be set to ?1?, indicating to the c t hat it may write the next task and its data to the modem.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 36 d/990/6 tso - transmit scrambler output this task, intended for channel set-up, enables the scrambler and transmits its output. when the modem has started the task the status 1 register bits will not change and hence these will not raise an irq. the c may write the next task and its data to the modem at any time and the scrambler output will stop when the new task has produced its first data. tsd - transmit short data block this task takes 4 bytes of data from the data bu ffer, calculates and applies a 16-bit crc and forms the fec for the 4 data bytes and the crc. this data is then interleaved and passed through the scrambler, if enabled, before being transmitted as a mobitex data block. once the modem has read the data bytes from the data buffer, the bfree and irq bits of the status 1 register will be set to ?1?, indicating to the c t hat it may write the next task and its data to the modem. note: in transmit mode the crc checksum circuit is in itialised on completion of any task other than null. 5.3.4.2.3 reset - stop any current action this task takes effect immediately, and terminat es any current task the modem may be performing and sets the bfree bit of the status 1 register to ?1?, without setting the irq bit. it should be used when v dd is applied to set the modem into a known state. note that due to delays in the internal circuitry, it will take approximately 3 bit times for any change to become apparent at the transmitter output. 5.3.4.2.4 task timings the device should not write to the command regi ster whenever the enable baseband bit is changed from ?0? to ?1? and for at least 2 bit times after the following: changing the tx/rx bit. resetting or after power is applied to the device. this is to ensure that the internal operation of the devic e is initialised correctly for the new task. note that this only applies to the command register, the other registers may be accessed as normal.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 37 d/990/6 figure 20 transmit mode timing diagram task typical time (bit-times) t1 time from writing first task (modem in ?idle? state) to application of first transmit bit to tx low pass filter any 1 t2 time from application of first bit of t7h 36 task to tx low pass filter until bfree tqb 24 goes to a logic ?1? (high) tdb 20 tsb 1 tsd 6 t3 time to transmit all bits of task t7h 56 tqb 32 tdb 240 tsb 8 tsd 72 t4 max time allowed from bfree going to a t7h 18 logic ?1? (high) for next task (and data) to tqb 6 be written to modem tdb 218 tsb 6 tsd 64
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 38 d/990/6 figure 21 receive mode timing diagram task typical time (bit-times) t3 time to receive all bits of task sfh 56 r3h 24 rdb 240 rsb 8 rsd 72 t6 maximum time between first bit of task sfh 14 entering de-interleave circuit and task r3h 18 being written to modem rdb 218 rsb 6 rsd 64 t7 time from last bit of task entering de-interleave circuit to bfree going to a logic ?1? (high) any 1
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 39 d/990/6 tx and rx low pass filter delay the previous task timing figures are based on the signal at the input to the rf sections (in transmit mode) or the input to the de-interleave buffer (in receive mode). there is an additional delay of about 2 bit times in both transmit and receive modes due to the tx/rx filtering and rf circuitry, as illustrated in the figure below. figure 22 low pass filter delay 5.3.4.3 control register this 8-bit write only register controls the response times of the receive clock extraction and signal level measurement circuits. control register $02 write bit: 7 6 5 4 3 2 1 0 agc control iq offset control frequency tracking (afc) control pll control the modem needs to make accurate measurements of the received signal level, dc offset, frequency offset and bit timing to achieve reasonable error rate s. accurate measurements, especially in the presence of noise, are best made by averaging over a relatively long time, however, in most cases the modem will be used to receive isolated messages fr om a distant transmitter and may be turned on for a very short time before the message starts to cater for this situation acquire bits 7 to 5 are provided in the command register ($01) which, when triggered, cause the modem to follow an automatic sequence designed to perform these measurements as quickly as possible. after these acquisition sequenc es have completed the circuits return to the mode as set in this register.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 40 d/990/6 control register b7, b6: agc control these two bits have no effect in transmit mode. in receive mode these bits set the response of t he agc circuit. the 'run' and 'max gain and run' settings allow the circuit to acquire and track incoming signals. b7 b6 setting action 0 0 max gain and hold agc set to maximum gain and held 0 1 hold* agc gain not updated by internal circuit 1 0 run agc tracks input signal 1 1 max gain and run agc set to maximum gain and tracks input signal * host may override agc setting by writing to $19 only when this setting is selected. control register b5, b4: i/q offset control these two bits have no effect in transmit mode. in receive mode, these set the ?normal? response of the i/q offset measuring circuits . the offset control is in two sections, an analogue 'coarse' setting and a digital 'fine' setting. the host may read and directly overwrite the coarse setting via registers $18 and $19. the coarse and fine settings will be overridden by the acquire i q offset command (bit 6 of co mmand register) which will go through a sequence of: reset (equivalent of reset task in command register) turn off receiver ?front end? run with tracking for 25 bits to correct i/q offset errors turn on receiver ?front end? and apply offset revert to normal setting (hold / fine / coarse) further details can be found in section 6.5.2 b5 b4 setting action 0 0 reset and hold i/q offset tracking reset and held 0 1 hold* i/q offset tracking held at current setting 1 0 fine tracking* i/q fine offset tracking 1 1 coarse tracking i/q coarse offset tracking * host may override coarse i/q offset by writing to registers $18 and $19 only when these settings are selected and bit 6 of command register is = '0'. control register b3, b2: frequency tracking (afc) control these two bits have no effect in transmit mode. in receive mode, they set the ?normal? response of the frequency tracking circuits. this setting will be temporarily overridden by the acquire afc command (b it 5 of command register) which will go through a sequence of: reset (equivalent of reset task in command register) run with fast tracking for 96 bits to correct frequency offset error run with slow tracking for 750 bits to follow any further frequency offsets revert to normal setting (hold / slow / fast) b3 b2 setting action 0 0 reset and hold frequency tracking reset and held 0 1 hold frequency tracking held at current setting 1 0 slow tracking frequency slow tracking 1 1 fast tracking frequency fast tracking
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 41 d/990/6 for mobitex systems, and most general purpose applications using the modem, these bits should normally be set to slow tracking after the host has activated the automatic sequence. the fast setting allows the modem to respond quickly without c intervention - although at the cost of reduced bit error rate versus signal to noise performance. note that the afc measuring system requires ?00? and ?11? bit pairs to be received at reasonably frequent intervals. the afc tracking will eventually fa il if ?1? or ?0? is transmitted continuously. control register b1, b0: pll control these two bits have no effect in transmit mode. in receive mode, they set the ?normal? bandwidth of the rx clock extraction phase locked loop circuit. this setting will be temporarily overridden by the acqui re bit clock command (bit 7 of command register) which will go through a sequence depending if a frame sync is being searched for (sfh or sfs task is started within 14 bits): frame sync search: no frame sync search: wide setting until frame sync is detected 16 bits of wide setting 30 bits of medium setting 30 bits of medium setting revert to normal setting revert to normal setting b1 b0 pll bandwidth suggested use 0 0 hold signal fades 0 1 narrow < 20ppm bit rate error systems 1 0 medium wide bit rate error or long preamble acquisition 1 1 wide quick acquisition the ?hold? setting is intended for use during signal fades, otherwise the minimum bandwidth consistent with the transmit and receive modem bi t rate tolerances should be chosen. the wide and medium bandwidth settings allow the modem to respond rapidly to fresh messages and recover rapidly after a fade without c intervention - although at the cost of reduced bit error rate versus signal to noise performance. note that the clock extraction circui ts work by detecting the timing of edges, i.e. a change from ?0? to ?1? or ?1? to ?0?. the clock extraction will eventually fail if ?1? or ?0? is transmitted continuously 5.3.4.4 mode register the contents of this 8-bit write only register control the basic operating modes of the modem: mode register $03 write bit: 7 6 5 4 3 2 1 0 irq enable invbit txrxn scren en pll lock irq enable dq irq enable main adc enable main dac mode register b7: irq enable - irqn output enable when this bit is set to ?1? the irqn chip output pin is pulled low (to v ss ) whenever the irq bit of the status register is a ?1?. mode register b6: invbit - invert bits this bit controls inversion of transmitted and received dat a. this allows for frequency inversions in the rf chain and has the effect of swapping i and q paths in both transmitter and receiver.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 42 d/990/6 mode register b5: txrxn - tx/rx mode setting this bit to ?1? puts the modem into transmit m ode, clearing it to ?0? puts the modem into receive mode. when changing from rx to tx there must be a 2-bit pause before setting a new task to allow the filter to stabilise. (see also baseband enable bit, section 5.3.5). note that changing between receive and transmit modes will cancel any current task. note also that this bit does not enable tx or rx sections of the cm x990 which must be enabled by separate control bits. mode register b4: scren - scramble enable the scrambler only takes effect during the transmission or reception of a mobitex data block, short data block and during a tso task. setting this bit to ?1? enables scrambling, clearing it to ?0? disables scrambling. the scrambler is only operative, if enabled by this cont rol bit, during tso, rdb, rsd, tsd or tdb, it is held in a reset state at all other times. this bit should not be changed while the modem is decoding or transmitting a mobitex data block. mode register b3: en pll lock irq - enable phase lock loop lost irq setting this bit to ?1? causes the irq bit of the stat us 1 register to be set to ?1? whenever the pll lock lost bit is set to 1. (the phase lock lost bit of status 2 register will also be set to ?1? at the same time.) mode register b2: enable dq irq - enable data quality irq in receive mode, setting this bit to ?1? causes the irq bit of the status 1 register to be set to ?1? whenever a new data quality reading is ready. (the dqrdy bit of the status 1 register will also be set to ?1? at the same time.) in transmit mode this bit has no effect. mode register b1 - 0: enable main adc / enable main dac when the respective bit is set to ?1? the main adc and dac are enabled, power may be saved by setting these bits to ?0? when the adc or dac are not needed. bit ?0? would normally only be set to ?1? when bit 5 is set to ?1?. bit ?1? would normally only be set to ?1? when bit 5 is set to ?0?. 5.3.4.5 status registers two status registers indicate events that may requi re action by the host. those marked as bold in the diagrams below will cause bit 7 of status1 (irq) to go high when they change from a 0 to 1. interrupts are enabled by setting bit 7 of the mode register ($03) to '1', the irqn pin will then be pulled low whenever the irq bit goes high. if the irqn line to the host is pulled low or if the host is polling for interrupts then status register 1 should be read first then optionally followed by reading status register 2. the irq bit will be cleared to a '0' when the stat us register containing the interrupt(s) is read. status1 $01 read bit: 7 6 5 4 3 2 1 0 irq bfree ibempty dibovf crcfec dqrdy moban packet detect status2 $03 read bit: 7 6 5 4 3 2 1 0 pll lock lost main pll in lock aux pll in lock tx pll in lock spc command complete aux adc conversion complete freq offset error iq offset complete
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 43 d/990/6 status 1 register, b7: irq - interrupt request this bit is set to ?1? by: the status 1 register bfree bit going from ?0? to ?1?, unless this is caused by a reset task or by a change to the mode register enable baseband or txrxn bits. or the status 1 register ibempty bit going fr om ?0? to ?1?, unless this is caused by a reset task or by changing the mode register enable baseband or txrxn bits. or the status 1 register dqrdy bit going from ?0? to ?1? (if dqen = ?1' ). or the status 1 register dibovf bit going from ?0? to ?1?. or the status 1 register packet detect bit going from ?0? to ?1? if the enable packet detect bit is set in the command register. or the status 2 register bits 7, 3, 2, 1 or 0 going from ?0? to ?1?. the host must read status 1 register first after detecti ng or looking for an interrupt condition. the irq bit is cleared to ?0? immediately after a read of the status register that caused the interrupt. in the case where 1 or more bits in status 2 register caus e an interrupt the irq bit is only cleared after reading status 2 register. if the irqen bit of the mode register is ?1?, t hen the chip irqn output will be pulled low (to vss) whenever the irq bit is ?1?. status 1 register, b6: bfree - data buffer free this bit reflects the availability of the data buffe r and is cleared to ?0? whenever a task other than null, reset or tso is written to the command register. in transmit mode, the bfree bit will be set to ?1? (als o setting the status 1 register irq bit to ?1?) when the modem is ready for the c to write new data to the data buffer and the next task to the command register. in receive mode, the bfree bit is set to ?1? (also se tting the status 1 register irq bit to ?1?) by the modem when it has completed a task and any data a ssociated with that task has been placed into the data buffer. the c may then read that data and write the next task to the command register. the bfree bit is also set to ?1?, but without setting the irq bit, by a reset task or when the mode register enable baseband or txrxn bits are changed. status 1 register, b5: ibempty - interleave buffer empty in transmit mode, this bit will be set to ?1?, also se tting the irq bit, when less than two bits remain in the interleave buffer. any transmit task written to the modem after this bit goes to ?1? will be too late to avoid a gap in the transmit output signal. the bit is also set to ?1? by a reset task or by a change of the mode r egister txrxn or enable baseband bits, but in these cases the irq bit will not be set. the bit is cleared to ?0? by writing a task other than null, reset or tso to the command register. note: when the modem is in transmit mode and the in terleave buffer is empty, a mid-level voltage (v bias ) will be applied to the tx low pass filter. in receive mode this bit will be ?0?.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 44 d/990/6 status 1 register, b4: dibovf - de-interleave buffer overflow in receive mode this bit will be set to ?1? (also setti ng the irq bit) when a task is written to the command register too late to allow continuous reception. the bit is cleared to ?0? by reading the status 1 register or by writing a reset task to the command register or by changing the enable baseband or txrxn bits of the mode register. in transmit mode this bit will be ?0?. status 1 register, b3: crcfec - crc or fec error in receive mode this bit will be updated at the end of a mobitex data block task, after checking the crc, and at the end of receiving frame head control bytes, after checking the fec. a ?0? indicates that the crc was received correctly or the fe c did not find uncorrectable errors, a ?1? indicates that errors are present. the bit is only cleared to ?0? by a reset task or by changing the enable baseband or txrxn bits of the mode register. in transmit mode this bit will be ?0?. status 1 register, b2: dqrdy - data quality reading ready in receive mode, this bit is set to ?1? w henever a data quality reading has been completed. the bit is cleared to '0' after reading the data quality register. immediately after a reset task, or a change in the enable baseband or txrxn bits to ?0?, the dqrdy bit may be set and generate an interrupt. the value in t he data quality register will not be valid in this case. status 1 register, b1: moban - mobile or base bit sync received in receive mode this bit is updated at the end of the sfs and sfh tasks. this bit is set to ?1? whenever the 3 bits immediately preceding a detected frame sync are ?011? (received left to right), with up to any one bit in error. the bit is set to ?0? if the bit pattern is ?100?, again with up to any one bit in error. thus, if this bit is set to ?1? then the received message is likely to have originated from a mobile and if it is set to ?0? from a base station. in transmit mode this bit is a logic ?0?. status register 1, b0: packet detect this bit indicates the status of the packet detect circuit and will be set to '0' when a packet is not present, as described in the description for command register bit b4. in transmit mode this bit will be ?0?. status 2 register, b7: pll lost lock 'pll lock lost' bit will be set to '1' whenever bits 4, 5 or 6 go from '1' to '0' since that bit was read as a '1' from status register 2, i.e. p ll lock lost bit is only set if lock has been gained, the host has read the register to confirm this and that bit subsequently goes from a '1' to a '0'. this will cause bit 7 of status1 to be set to '1' only if bit 3 of the mode register ($03) is set to '1'. this bit will be cleared to ?0? immediately after reading the status 2 register. status 2 register, b6-b4 pll in lock ( main / aux / tx ) bits 6 to 4 represent the lock status for the corresponding pll at the time of the read of status 2 register. a '1' indicates the pll is in lock, a '0' indicates that the pll is not in lock. buffer circuitry will prevent changes in the lock status being lost while this register is being read.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 45 d/990/6 status 2 register, b3: special command complete when operating a special command the 'spc command complete' bit will be set to '1' when a command has finished and any associated data can then be read out. the correct sequence to initiate a special command is to load any required data into the specia l data registers $1b to $1e then issue the special command by writing to the special command regist er $1a. having issued a special command the host must not read or write to the special command or dat a registers ($1a to $1e) until it has completed. reading register status 2 will clear this bit to '0'. status 2 register, b2: aux adc conversion complete 'aux adc conversion complete' bit will be set to '1' when all enabled adc channels have been converted. this bit will not be set if continuous conversion is selected, the host may read the latest conversion for each channel as required. reading register status 2 will clear this bit to '0'. status 2 register, b1: frequency offset error during rx mode the cmx990 continuously compares the local reference clock frequency against the received rf signal frequency. if these two frequencies dev iate by more than the limit set by the host (see section 5.3.8.3), the frequency offset error bit will be set to '1'. this bit will be cleared to '0' by reading register status 2. by default the e rror limit is set so that this bit never gets set. this default value can be changed by issuing a special command to the cmx 990 (see section 5.3.8). for further details on frequency measurements see section 5.3.12.1. status 2 register, b0: iq offset complete ?iq offset complete' bit will be set to '1' when the sequence to estimate the iq offsets of the receive channel has completed. during the offset acquisi tion sequence the received signal will be unreliable. 5.3.4.6 data quality register data quality register $02 read bit: 7 6 5 4 3 2 1 0 data quality reading (0-255) this is intended to indicate the quality of the rece ive signal during a mobitex data block or 30 single bytes. in receive mode, the modem measures the ?quality? of the received signal by comparing the actual received zero crossing time against an internally gener ated time. this value is averaged over 240 bits and at the end of the measurement the data quality r egister and the dqrdy bit in the status 1 register is updated. note: an interrupt will only occur at this time if the enable dq irq bit = ?1?. to provide synchronisation with data blocks, and henc e ensure the data quality register is updated in preparation to be read when the rdb task finishes, the measurement process is reset at the end of tasks sfh, sfs, rdb and r3h. in transmit mode all bits of the data quality register will be ?0?. figure 23 shows how the value (0-240) read from the data quality register varies with received signal to noise ratio. note that the signal-to-noise ratio show is the post detection signal to noise and that this is different from the s/n measured in the rf section.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 46 d/990/6 figure 23 typical data quality reading (after 240 bits) vs baseband s/n (noise in bit rate bandwidth) 5.3.5 power control the following registers control individual power-up state of the indicated blocks. note: other sections of the device have the power control bits included in t he control registers for those blocks. blocks are disabled and in the zero power state when the associated control bit is '0'. power up 1 $04 write bit: 7 6 5 4 3 2 1 0 enable clock enable baseband v reg enable op1 op2 rx if rx rf1 rx rf2 tx rfif if the enable clock is set to '0' the on chip clock bu ffer will be disabled, the clock buffer must be enabled if setting reset (bit 3 of $05) or if any of the internal circuits are powered up apart from those controlled by the 'v reg', 'vbias' and 'op1 op2' bits. when the clock enable bit is changed from 0 to 1, the clock is enabled directly, which may cause erroneous operation if refclk (pin 53) is changing at the same time. this problem will not happen if the clock pll is being used (i.e. the ?clock control regi ster? has a value other than $18). if not using the default value it is recommended that the required value is written to the ?clock control register? before the ?enable clock bit? is set. alternativly if $18 is to be used a reset command should be written ($05, bit 3) following the ?enable clock bit?. it will be noted that t he reset does not effect the ?enable clock? bit or the ?clock control register? (see section 5.3.3). the enable baseband bit controls the data packeting and clock extraction circuits, this must be set to '1' before writing to any other register. if v reg bit is set to '0' an internal circuit will hold the nominal 2.5v supply pins at approximately 2v for data retention only. for normal operation the host mu st set this bit to '1' before enabling any other circuitry. if an external supply provides the nominal 2.5v then the v reg bit should be set to '0'. see section 4.5 for more details.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 47 d/990/6 when the op1 op2 bit is low both op 1 and op 2 amp lifiers are disabled the op1t and op2t pins will become high impedance inputs to adc2 and adc3 res pectively. when set to ?1? both op-amps are enabled. rx if bit enables the circuitry from the if in pin to the differential i and q outputs to the baseband. rx rf1 bit enables the circuitry from the rf in a and rf in b pins to the output of the 1st mixers. rx rf2 bit enables the circuitry from the output of the 1st mixers to the if out pin. tx rfif bit enables all the transmit rf and if circuits from the differential i and q inputs to the tx rf interface pins. power up 2 $05 write bit: 7 6 5 4 3 2 1 0 aux dac3 aux dac2 aux dac1 aux dac0 reset lna on (external) preserve registers vbias the vbias control bit must be enabled early enough so t hat the output is stable before any of the other circuit blocks are enabled as this circuit takes some time to stabilise after being enabled. setting the reset bit to '1' will not change the vbias bit. if set to '1' the preserve registers bit will preser ve most user settings programmed via the special command register, e.g. rx channel filter coeffici ents and non assigned memory. in rx mode the agc, offsets and timing estimates of the received signal will be lost after a reset event. lna on bit directly controls the lna on pin and does not control any internal analogue circuitry. any time delay for the external circuitry to stabilise must be taken into account when controlling this bit. this control bit will be cleared to '0' after a power on reset or if the reset bit is set to '1'. whenever a '1' is written to the reset bit all regist ers will be cleared to '0' apart from the clock control register, bit 7 of the power up register will be set to 1. bit 5 of the power up 1 register and bits 1 and 0 of the power up 2 register will remain in their previous stat e. this will put all internal circuits in an inactive and power saved state except for the 'clock enable' bu ffer which remains at '1' so that the device may respond to the tcxo clock. the 'v reg', 'prese rve registers' and 'vbias' bits will be unchanged. to ensure a clean exit from the reset condition the reset bit should be set to '0' before any other circuitry is enabled. i.e. to enter reset write '000010xx' to $05. to exit reset write '000000xx' then 'xxxx0xxx', where 'x' is the desired condition for the aux dacs, lna on, 'preserve registers' and 'vbias' bits. the host may then program the rest of the device to the desired configuration. the aux dac0-3 bits control the relevant auxiliary dac. 5.3.6 auxiliary dac and adc 5.3.6.1 aux dac 0-3 $08-0f auxiliary dac data registers (write only) $08-09 aux dac 0 auxiliary dac 0 data register lsb - msb $0a-0b aux dac 1 auxiliary dac 1 data register lsb - msb $0c-0d aux dac 2 auxiliary dac 2 data register lsb - msb $0e-0f aux dac 3 auxiliary dac 3 data register lsb - msb $08, $0a, $0c, $0e bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 dac data [1:0] $09, $0b, $0d, $0f bit 7 6 5 4 3 2 1 0 dac data [9:2]
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 48 d/990/6 there are two input registers for each of the four auxilia ry dacs. writing to the lsb register writes the two least significant bits of dac data. writing to the msb register writes the eight most significant bits of dac data and then passes all ten bits to the appropriate dac input. if the msb register is written while the lsb register is left constant, the converter may be treated as an 8-bit dac. 5.3.6.2 ramdac control $10 auxiliary ram dac control register bit: 7 6 5 4 3 2 1 0 inc aux ram address en aux ram access ram dac scan rate [0-7 = /1024 to /8] scan direction en auto cycle en ram dac setting bit 7 high will cause read operations to the aux iliary dac ram to increment the address pointer. setting this bit low causes write operations to increment the address pointer. bit 6 enables access to the auxiliary dac ram. se tting bit 6 low resets the ramdac address pointer. bits 5 to 3 control the rate at which the ram dac address pointer changes: bit 5 bit 4 bit 3 rate of change 0 0 0 bclk/1024 0 0 1 bclk/512 0 1 0 bclk/256 0 1 1 bclk/128 1 0 0 bclk/64 1 0 1 bclk/32 1 1 0 bclk/16 1 1 1 bclk/8 note: bclk = base-band clock, see section 5.3.10. bit 2 controls the direction of the memory scan oper ation. setting this bit high will cause the memory address pointer to increment to the top location, setti ng this bit low will cause the memory address pointer to decrement to the bottom location. if this bit is changed while the memory is being scanned, the current scan will complete before the new state of this bit takes effect. when bit 1 is set high, the memory address pointer continuously increments to the top location and then decrements to the bottom location. bit 0 controls whether dac0 is driven by the ram (when set high) or the aux dac 0 register (when set low).
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 49 d/990/6 5.3.6.3 auxramdata1/2 $14-17 auxiliary dac memory i/o access addresses $14 bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ram data [1:0] $15 bit 7 6 5 4 3 2 1 0 ram data [9:2] $16 bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ram data [1:0] $17 bit 7 6 5 4 3 2 1 0 ram data [9:2] these four address locations allow access to the 64 x 10-bit ram. the contents of this ram can be pre- loaded with a table of values that can be automatically sent to the auxiliary dac0 in either a single cycle or continuous mode. therefore the ram can be us ed in conjunction with dac0 to enable user defined profile power ramping of an exte rnal rf power transmitter stage. the ram contents are addressed increm entally by first setting bit 6 of ramdac control register. while this bit is low, the ram address pointer is held reset. the first two data words are written by writing to addresses $14 to $17 in order. accessing location $17 pos t-increments the address pointer. bit 7 of the ramdac control register determines whether a r ead or write operation will increment the ram address pointer. further write operations to addresse s $14 to $17, will load the next two locations. all locations are accessed incrementally; further accesse s to this port while bit 7 of the ramdac control register is active are not valid and may cause data loss. 5.3.6.4 aux adc 0-5 data registers $08-13 read $08-09 aux adc 0 auxiliary adc 0 data register lsb - msb $0a-0b aux adc 1 auxiliary adc 1 data register lsb - msb $0c-0d aux adc 2 auxiliary adc 2 data register lsb - msb $0e-0f aux adc 3 auxiliary adc 3 data register lsb - msb $10-11 aux adc 4 auxiliary adc 4 data register lsb - msb $12-13 aux adc 5 auxiliary adc 5 data register lsb - msb $08, $0a, $0c, $0e, $10, $12 bit 7 6 5 4 3 2 1 0 x x x x x x adc data [1:0] $09, $0b, $0d, $0f, $11, $13 bit 7 6 5 4 3 2 1 0 adc data [9:2] these registers enable the user to inspect the conver sion value for each of the six auxiliary adcs. there are two read registers per adc, one to obtain the two l east significant bits of the data, the other for the eight most significant bits. reading these registers does not affect the adc c onversion cycle. reading the msb register directly reads the adc output and simultaneously causes the two bits in the lsb register to be written to a holding register. this hol ding register is read when the lsb register is read. this mechanism is necessary to allow the us er to read msb and lsb data from the same adc conversion cycle. if only the msb register is read, the converter can be considered as an 8-bit adc. if a 10-bit conversion is required, the msb register must be read first.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 50 d/990/6 5.3.6.5 aux control1 $11 write bit: 7 6 5 4 3 2 1 0 0 0 enable adc 5 enable adc 4 enable adc 3 enable adc 2 enable adc 1 enable adc 0 this register controls which adc channels are conv erted. these bits may be changed at any time, but will only update the active state of the adc c hannel for the next time it is converted. 5.3.6.6 aux control2 $12 write bit: 7 6 5 4 3 2 1 0 dac ram polarity reset dac rams 0 0 0 conversion rate enable cont conversion start conversion if bit 6 is set to '1' the ram associated with dac 0 is rese t, if bit 7 is high the ram is reset to all 1's, if bit 7 is low the ram is reset to all 0's. this feature can be used to avoid programming every ram location when short ramp profiles are required. bit 2 selects the conversion rate of the auxiliary a dc. if set low, the adc will be clocked at (base-band clock/16), giving a conversion time of 176 base- band clock periods per enabled channel. setting this bit high halves the adc clock rate and doubles the conversion time. the first sample after enabling an auxiliary a/d sequence will take 3 conversion times to complete, each subsequent conversion will take 1 conversion period. for base-band cl ock control - see section 5.3.10. setting bit 1 high will cause each enabled adc channel to be converted continuously. setting bit 0 high will cause a single conversion of all enabled adc channels. this bit is automatically set low when the adc conversion has been completed. note that bi t 0 only has an effect when bit 1 is set low. 5.3.7 analogue setup analogue setup 1 $18 write bit: 7 6 5 4 3 2 1 0 set tx attenuation: '11' = 0db, '10' = 10db '01'= 20db, '00'= 20db coarse rx i offset, '10000' = mid value '00000' = max -ve offset, '11111' = max +ve offset analogue setup 2 $19 write bit: 7 6 5 4 3 2 1 0 set rx agc: '11'= 40db, '10'= 25db '01 =10db, '00' = -5db coarse rx q offset, '10000' = mid value '00000' = max -ve offset, '11111' = max +ve offset see section 5.3.11 for descrip tion of tx attenuation. the rx agc may be controlled by the host if the agc cont rol ($02, b7-b6) is set to ?hold? mode. in this mode the rssi value calculated by the cmx990 will a ssume the last value of agc calculated by the cmx990. if the host writes a new value the cmx990 r ssi circuits are not aware of this value and the host must apply an appropriate correction to the rssi r eported by the cmx990. note that the state of the agc can be read from $19, b7-b6 (see below). a possible sequence for manual updating the agc could be:
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 51 d/990/6 i. set agc ?hold? mode ($02 b7-b6 = ?01?) ii. read analogue setup 2 and store agc value iii. write new agc value to analogue setup 2 iv. read rssi. v. if new value of agc is different from the st ored value apply appropriate correction to rssi value vi. repeat steps iii to v as required. the rx i and q offsets are the values applied to the har dware to correct for dc offsets. the offset can be measured automatically by the cm x990 (see sections 5.3.4.2 and 5. 3.4.3). analogue setup registers allow the offset values to be read or written by t he host. note that writing to these registers is only possible in certain conditions. an overview of dc calibration is given in section 6.5.2 analogue setup 1 $18 read bit: 7 6 5 4 3 2 1 0 x channel filter overflow coarse rx i offset, '10000' = mid value '00000' = max -ve offset, '11111' = max +ve offset bit 6 is set to '1' when the receive channel filters have a numerical overflow. this bit is reset to '0' after this register is read. this bit does not generate an interrupt and is intended for test purposes only for evaluating custom receive filter coe fficients (see section 5.3.8.1). bits 5 to 0 indicate the current coarse offset correction in the receive i path. analogue setup 2 $19 read bit: 7 6 5 4 3 2 1 0 agc setting 0-3 coarse rx q offset, '10000' = mid value '00000' = max -ve offset, '11111' = max +ve offset bits 7 to 6 indicate the current gain setting of the agc ci rcuit. bits 5 to 0 indicate the current coarse offset correction in the receive q path. 5.3.8 special command functions special command (spc) $1a write bit: 7 6 5 4 3 2 1 0 special command special data0 $1c-1b read and write bit: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 msb data lsb data special data1 $1e-1d read and write bit: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 msb data lsb data the 8-bit value written to the special command (spc) register instructs the modem to perform special tasks such as loading coefficients or reading receive va lues. when executing a special task that requires input data, the data should be loaded into the specia l data 0/1 registers before writing the special command. when the special command has completed, the 'spc command complete' bit will be set to '1' and the host can read out any reply data from the spec ial data 0/1 registers. if the internal circuits
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 52 d/990/6 read the spc register as a non-zero value, they w ill try to complete the task when there is a gap in processing. input data returned data function cmd no. (hex) data 0 $1c $1b msb lsb data 1 $1e $1d msb lsb data 0 $1c $1b msb lsb data 1 $1e $1d notes null 00 - - - - no command - do nothing set address 01 address - - - address1 = address set tx filter 09 - - - - address1 = tx filter address set rx channel filter 0a - - - - address1 = rx channel filter address set rx gauss 0b - - - - address1 = rx gauss filter address poke(addr) 0c address data - - *address=data user channel filter 15 - - - - loads rx channel filter from data at address1 set bt 1a data - - - set bt bt = 0.3 is default setting set bt = 0.5 1b - - - - tx and rx with bt = 0.5 set afc limit 1c limit - - - view rx eye 1d - - - - for rf test set up set decode threshold 18 offset - - - set data decode threshold level. default = 2400 set rssi averaging 1f data - - - set n and f values see sections 5.3.8.6 and 5.3.12.2 notes: *address = data in memory pointed to by 'address'. 5.3.8.1 alternative channel filters it is possible to load alternative filters in the cmx990. the transmit data filter, the receiver channel filter and receiver data filter are all progra mmable. for further details contact techsupport@cmlmicro.com. 5.3.8.2 transmitter bt opti ons (special command $1a, $1b) in addition to the ability to completely re-program the filters three pre-programmed filters are available in the cmx990 offering bt = 0.27, bt = 0.3 or bt = 0.5. the default operation of the cmx990 is bt=0.3. th is can be changed using special command $1a which should have data in data 0 ($1c, $1b). the following setting are allowed: data 0 value result 0 bt = 0.3 1 bt = 0.5 2 bt = 0.27 a simplified command to select bt = 0.5 is specia l command $1b which does not require a data value. 5.3.8.3 afc limit (special command $1c) this special command allows the limit at which a frequency error measurement will trigger an interrupt. for more details see section 5.3.12.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 53 d/990/6 5.3.8.4 view rx eye (special command $1d) - receiver set-up to assist in evaluating the performance of the rf and if circuits the user can enable a special test mode to observe the base-band eye from the receiver. th is gives a good measure of the overall receiver performance and can be useful to give a rapid visual indi cation of the effects of disturbing factors such as frequency offset, if filter changes, rf levels etc. the ideal rx eye patterns are shown in figure 14. during 'view rx eye' mode pins 45 and 46 temporarily become outputs and are driv en by the receive eye signal differentially. these 2 pins should have an ex ternal rc filter of 100kohm and 33pf on each line to analogue ground for operation at 8kb/s (scale the c apacitor values inversely with bit rate). to enter the 'view rx eye' mode, first set up the transmit and receive paths as required, ensure that auxiliary adc4 and adc5 are powered down (these f unctions normally use pins 45 and 46), then write the following to the cmx990 receiving the signal: address data $03 xx0xxx11 enable main adc and main dac $3f 11101010 enable routing to pins 45 and 46 $1a 00011101 start special command $1d where 'x' represents the user's preferred settings. the oscilloscope or other instrument displaying t he received eye may need a trigger signal synchronised to the data, especially in degraded signal conditions. ideally this should be taken from the device generating the transmitted signal, however this is some times not available (e.g. when receiving a signal remote from the transmitting system). in this case the irq from the cmx990 can be used while it carries out successive rsb tasks on the received data. to exit the 'view rx eye' mode the cmx990 should be reset. 5.3.8.5 set decode threshold (special command $18) this a threshold within the decoder which optimises performance of the receiver for a particular bt. the required threshold is set for a particular level of data filtering. as can be seen in figure 14 with a bt=0.3 significant inter-symbol-interferene (isi) is introduced causing a closing of the data ?eye?. the amount of this ?eye? closing is compensated with this threshold. the default threshold (2400-decimal) is optimal for bt=0.3. increasing bt will require a lower threshold, e.g. with bt=0.5 a threshold of 1500 (decimal) is recommended. 5.3.8.6 rssi averaging this command sets the amount of averaging used in calculating the rssi measurement (see section 5.3.12.2). the $1f command offers the following averaging options: data 0 value n and f values averaging time 0 n=2048,f=16 64ms 1 n=1024,f=32 32ms 2 n=512,f=64 16ms 3 n=256,f=128 8ms 4 n=128,f=256 4ms 5 n=64,f=512 2ms 6 n=32,f=1024 1ms 7 n=16,f=2048 0.5ms 5.3.9 local oscillator synthesisers two integer-n synthesisers are provided, one as the ma in rf synthesiser (main pll), which provides the tuneable frequency to enable channel selection, and the other (aux pll) for the generation of lower
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 54 d/990/6 frequency for mixing to / from if and baseband. these two synthesisers are fully programmable, via the processor interface, to any frequency in the range 600 mhz to 2 ghz and 150 mhz to 250 mhz respectively. both the synthesised frequencies are in ternally divided down. the main rf frequency is divided by two for use in the offset loop in the tr ansmitter and also for the image reject mixer in the receiver. note that, in order to obtain quadrature signals for the image reject mixer, both the rising and falling edges of the vco generated signal are used; it is important, therefore, that the vco produce a waveform that is as close as possible to a mark to space ratio of one. the second synthesiser is optionally divided by 2 or 4 for the transmitter and divided by 4 for the receiver. both synthesisers are phase locked loops (plls) and ut ilise external vcos and loop filters. the phase noise of the vcos should be adequate for the application with particular attention paid to the performance of the main vco. it will be noted that as the cmx 990 includes an internal divide-by-two in the lo path the pll phase noise will be improved by approximately 6db. the loop filters will need to be designed as required based on switching bandwidths, vco gain etc. the cmx990 phase detectors are of the phase- frequency type with a high impedance charge pump output requiring just passive components in the loop filter. as a result standard design equations for a type ii pll can be used to select loop filter components. lock detect functions are built in to each synthesiser and the status reported to the host processor. in particular, a transition to out-of-lock can be detect ed and communicated via an interrupt to the processor if required; this can be important to ensure that the transmitter cannot falsely tr ansmit into other bands in the event of a fault condition arising. the minimum step size is programmable by setting the re ference division ratio; to minimise the effects of phase noise this should be kept as high as possible, particularly on the main rf synthesiser. for mobitex, the maximum this can be set to is 25 khz as this is governed by the 12.5 khz channel spacing and the subsequent divide-by-2 of the generated frequency. note that if it is required to select a frequency that is 6.25 khz offset from a convenient division of the main frequency (although still with 12.5 khz channel spacings), it is better to keep the step size at 25 khz but slightly offset the reference oscillator. in this way the phase noise and lock time performance will not be compromised. each synthesiser is set up using two registers, an ?m? register that sets the division value of the input reference frequency to the comparison frequency (step size ), and an ?n? register that sets the division of the required synthesised frequency from the ex ternal vco to the comparison frequency. in the main pll the vco frequency is pre-scaled by 2 prior to being divided by n, therefore there is a factor of 2 in the formula that yields a requir ed synthesised frequency. the equations for the main and auxiliary synthesisers are: f main = (2 x n main / m main ) x f ref n main > 1023 m main > 1 f aux = (n aux / m aux ) x f ref n aux > 7 m aux > 1 where f ref is the reference oscillator frequency ref clk. main and aux pll and rf set up input the main and aux pll circuits have control registers as listed below. writing to the least significant 8 bits will trigger the circuit to update the dividers with the new multi byte value. whenever the enable bit is low the divider circuit will be in the inactive 'zero power ' (zp) mode. to enter normal operation from zp mode the msb (including the enable bit) is written, the lsb would be written last, this would simultaneously enable the pll and load the divider ratio - lock may ta ke longer when exiting zp mode. to enter zp mode only the msb need be written, double buffering will not be used for this control line - a simple set / reset latch will store the 'enable' value, set from the output of the 2nd buffer, reset from the inverted output of the 1st buffer. the main and aux pll will control their outputs to the required quiescent value when shutting down. output one buffered digital output line from each pll will indicate when the relevant pll is in lock, this output is not synchronised. '1' = pll enabled and in lock, '0' = all other conditions (including disabled zp state).
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 55 d/990/6 these lock outputs are available in t he status register in the host inte rface block and can optionally cause an external interrupt to occur. see section 5.3.4.5 for a description of interrupt operation. main pll m divider $21-20 write bit: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 main pll enable tx lo div tx mix filter msb lsb tx lo div controls a divide by 2 stage in the tx lo clock path, '1' = div by 1, '0' = div by 2. tx mix filter controls the post tx mixer filter response, '1' = hi (118mhz), '0' = low (83mhz). see also section 5.3.11. note: when writing synthesiser divider values the l sb must be written last to trigger the update. main pll n divider $24-23-22 write bit: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 sign 0 0 tx vco charge msb nsb lsb in rx 'sign' controls the polarity of the rx if summer which is part of the image reject mixer in the receiver, a '0' = summation, '1' = subtraction. this allows the image reject mixer to be used for high-side or low-side injection. in tx 'sign' controls the slope of the tx p ll, '0' for a positive slope, '1' for negative slope. tx vco charge controls the tx vco charge circ uit, '1' = charge to 1/2 vdd, '0' = no charge. see also section 5.3.11. note: when writing synthesiser divider values the l sb must be written last to trigger the update. aux pll m divider $26-25 write bit: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 aux pll enable tx if filter msb lsb note: when writing synthesiser divider values the l sb must be written last to trigger the update. bit 6 bit 5 tx if filter setting 0 0 90 mhz 0 1 80 mhz 1 0 45 mhz the 'tx if filter' bits control the tx if filter frequency: (see also section 5.3.11.) 1 1 40 mhz aux pll n divider $28-27 write bit: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 tx if div 0 msb lsb the 'tx if div' bit controls a divide by 2 stage in the tx if clock path, '0' = divide by 1, '1' = divide by 2. note: when writing synthesiser divider values the l sb must be written last to trigger the update.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 56 d/990/6 5.3.10 clock control this register controls the reference dividers block. the clock input to the ref clk pin can be used to give a variety of bit rates from common clock rates, see examples given in the tables below. the clock control architecture is shown in figure 24. ref clk (mhz) a , ref clock divider base freq (mhz) base freq (mhz) vco freq (mhz) b , base- band divider base- band clock bit rate 4.8 2 2.4 2.4 76.8 8 9.6 4000 12 5 2.4 2.4 76.8 4 19.2 8000 16.8 7 2.4 2.4 76.8 2 38.4 16000 19.2 8 2.4 2.88 92.16 8 11.52 4800 21.6 9 2.4 2.88 92.16 4 23.04 9600 14.4 5 2.88 notes: 1. bit rate = (ref clk) / (75 x a x b). bit rate should only be set from 4kb/s to 16kb/s. 2. the frequency of the signal at the ref clk pin must be in the range 3.8mhz to 24mhz. 3. the base frequency resulting from the division of the ref clk signal must be in the range 1.9mhz to 3.0mhz. 4. the clock rate to the synthesizers is always the frequency of the signal at the ref clk pin. divide by a divide by b phase detector divide by 32 divide by 10 ref clk input (3.8 to 24mhz) vco frequency (base frequency x 32) baseband clock (2400 x bit rate) sample clock bypass selected if register $29 has value $18 base frequency (1.9 to 3.0mhz) figure 24 programmability of clock circuits clock control $29 write bit: 7 6 5 4 3 2 1 0 b, base-band divider, 2 - 15 (0000 = illegal state, 0001 = see note 3) a , ref clock divider, 1 - 15 (0000 = illegal state, 1000 = see note 3) notes: 1. the value '0000' should not be programmed for 'a' or 'b'. 2. after power-up this register will be reset to $18. 3. if the ref clk is 19.2mhz and the required bit rate is 8000b/s then the clock control register can be programmed with $18. 'b' should only be set to '0001' fo r this condition. this is the default state of this register and is also the minimum power condition.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 57 d/990/6 5.3.11 transmitter control bits various control bits for the o-pll transmitter are incl uded in several diverse registers. details of their operation is included in this section so all related function can be seen together. the input to the o-pll mixer contains a variable a ttenuator. b7 and b6 in analogue setup 1 ($18, section 5.3.7) control the setting of the attenuator. steps available are 0db, -10db and ?20db. the attenuator is designed to allow the mixer to be operated in it?s linear range (therefore minimising spurious output) during normal operation. to allow locking of the l oop at minimum output power the attenuator can be switched to the 0db setting thereby providing maximum sensitivity. the ?tx if div? bit (b7, $28, section 5.3.9) controls the divider providing the local oscillator to the i/q modulator section. typical operati on of the cmx990 uses a 180mhz aux local oscillator. this will be divided by two to give a 90mhz txif if ?tx if div?=0. if ?tx if div?=1 a further division is applied to achieve a txif of 45mhz. this ?tx if div? therefor e effectively selects the tx mode (45mhz or 90mhz) for the tx operation of the cmx990. note that this bit does not effect the receiver i/q demodulator which has a fixed divide by 4 between the aux lo and the i/q demodulator. the ?tx vco charge? bit (b4, $24, section 5.3.9) allo ws the loop filter of the o-pll to be pre-charged to vdd/2 through a resistive divider network of 10k . this overcomes potential problem of the o-pll locking to an image of the txif if the vco used in the o- pll has a wide tuning range. further details can be found in section 6.4.1. the tx mix filter (b5, $21, section 5.3.9) controls the filter following the o-pll mixer. this filter can be set for cut-off frequencies of 83mhz for txif around 45mhz or 118mhz for txif around 90mhz. in practice the roll-off of this filter is quite slow and t he loop will lock successfully with either filter selected for either 45mhz or 90mhz txif operation (note this very different from the case with the ?tx if filter? discussed below) . the ?tx if filter? bits (b6 b5, $26, section 5.3.9) a llow the selection of a filt er between the output of the i/q modulator and the o-pll phase detector. selecting t he correct bandwidth is very important for correct operation of the loop. for txif around 90mhz the ? 90mhz? filter should be used, for txif around 45mhz the ?45mhz? filter should be used. the ?40mhz? and ? 80mhz? settings are provided if a little bit more rejection is required or a slightly different if is us ed (i.e. just below 45mhz or 90mhz). if the 90mhz filter is selected when using the ic in 45mhz mode the modulation spectrum will be severely degraded. this is due to harmonics of the txif signal getting into the phase detector. if the 45mhz filter is used with the ic in 90mhz mode then it is likely that the o-pll w ill not lock to the desired output frequency. this is because the loop reference frequency (in this case 90mhz) is not present as it has been filtered out prior to the phase detector input. the ?sign? bit (b7, $24, section 5. 3.9) controls the slope of the txpll charge pump output. with ?sign? = ?0? the vco should have a positive slope (i.e. a increas e in charge pump voltage results in an increase in frequency). with the ?sign? bit set to ?1? the vco slope should be negative. note that this bit also controls the polarity of the image reject mixer in the rece iver so in some circumstance might need to be changed between tx and rx operation. also it should be noted that the operation is dependant on the frequency change present to the phase detector input and this might be inverted by the offset mixing operation. this happens in the case of high-side frequency conversion in the o-pll. consider the case of figure 17, specifically a transmission of 819mhz with a 90mhz tx if. in this case the lo is 1818mhz, which after the divide by 2 is 909mhz applied to the o-pll mi xer. so the offset mixer performs 909-819=90mhz. now consider the case that vco frequency changes due to an increase in the vco tuning voltage, just for explanation of the effect, to 820mhz. it this case the vco follows the normal characteristic of an increase in tuning voltage resulting in an increase in the frequency (i.e. positive slope). now the o-pll mixer performs subtraction of 909-820=89mhz. so 89mhz appears at the phase detector not the expected 91mhz. in this case the effective slope of the vco is changed by the action of the mixer and negative polarity must be selected ? even though the vco itself is positive polarity.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 58 d/990/6 a further degree of flexibility is offered by the ?invbit? (b6, $03 section 5.3.4.4). this bit allows the polarity of the data to be inverted so that the correct polarity of modulation is always achieved, i.e a data ?1? can be set as a positive frequency shift or a negative frequency shift as the application requires. note that the ?invbit? also affects the receiver so may need to be changed between tx and rx in some circumstances. the ?tx lo div? (b6, $21, section 5.3.9) enable t he divide by two in the tx lo path (see figure 1). normal operation is with the divider active so the tx lo matches the rx lo which always has the divide by 2 active as this is part of the image reject mixer st ructure. the ability to switch off the divide by two is useful if an external mixer is used in the receiver. in this case the input to the rx mixer is likely to be at the desired mixing frequency (i.e. not tw ice that frequency) so it is helpful to be able to select this operation in the o-pll loop. this is discussed further in section 6.5.3. 5.3.12 other transceiver functions 5.3.12.1 frequency offset frequency offset $04 read bit: 7 6 5 4 3 2 1 0 rx measured rf frequency offset (-64 to 63) good data the 2's complement number read from bits 7 to 1 represents the estimate of the frequency error between the transmitter and receiver carriers. this value is onl y valid if bit 0 = '1'. if bit 0 = '0' the rf frequency offset will not be computed and bits 7 to 1 will hold the last value calculated. the scaling of this value alters with selected bit rate. with 8kbps the sca le is 19hz per bit, for 4kbps 38hz per bit and 16kbps 9.5hz per bit. intermediate values can be calcul ated by interpolating between the above values. the measured frequency offset can be less accurate when receiving a modulated signal with a large offset between the tx and rx frequencies as it becomes distorted by the band edges of the if filter. in this case, the reading may be approximately 10% in e rror. this error is less pronounced when receiving a carrier only with the same tx / rx frequency offset error. 5.3.12.2 signal strength signal strength $05 read bit: 7 6 5 4 3 2 1 0 rx measured signal strength rssi (0-255) the value read from this register represents the latest estimate of the rssi as the number of db above a level of approximately -150 dbm. the absolute scali ng of this will vary depending on gain of external components and input matching arrangements. the absol ute scaling should be evaluated for a particular design however the rssi is designed to work over at least ?113dbm to ?63dbm with typical external gains. the rssi value is averaged over a number of samples of the received data. this is to reduce variability due to noise and achieve a result with less fluctuation. thus the rssi algorithm computes the sum of n values, where each value is pre-multiplied by a fa ctor f. to obtain the same measured rssi value presented in this register for different values of n, the user must ensure that n/f is a constant. default values of n and f are n=2048 and f=16. these val ues of n and f can be changed using special command $1f (see section 5.3.8.6). the sample rate is 32khz so one sample is 1/32000=31.25 s. thus with n=2048 the averaging time is 2048*(1/32000)=64ms and the minimum averaging time is 16*(1/32000) = 0.5ms (see section 5.3.8.6 for a full table of values).
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 59 d/990/6 the rssi algorithm runs continuously while the rece iver is operating. the register is updated each time the specified number of averages has been completed. the register is updated within 31.25s after the last data sample. the new averaging period starts 31.25 s after the end of the pervious averaging period. this is shown graphically in figure 25. during the update period of 31.25 s the precise time the data is updated is not defined however the cmx990 ensures the data will always be valid (i.e. it will not produce erroneous values during an update). with the cmx990 operating in a particular state the update point will generally be the same so sampling rssi at the maximum rate for a particular sample window will always provide the next sample. for example with n= 64 the update rate is (64+1) * 1/32000 = 2.03125ms. reading the register at this rate will always provide the next value. averaging window (n samples) 31.25s x x+1 rssi value from period x-1 rssi value from period x figure 25 rssi timing see also section 6.5.6.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 60 d/990/6 6 application notes 6.1 general the cmx990 chip is a modem and rf system desi gned for wireless data modem applications. the chip addresses the needs of various data systems, bot h product standards and regulatory requirements, including: ? mobitex interface standard (mis) ? european r&tte ( based on en 300 113 or en 300 220) ? fcc limits (47 cfr parts 2 and 90) details of techniques to meet these requirements can be found in following sections along with general discussion of how to design with the cmx990. the firs t sections ( 6.2, 6.2.3, 6.2.4 and 6.3 ) detail the data formatting offered by the cmx990. operation is compliant with the mobitex system however the cmx990 is configurable and the data format can be usefully used for many packet data modems. sections 6.4 and 6.5 focus on aspects of the rf operation of the cmx990. 6.2 crc, fec, interleaving and scrambling information: 6.2.1 crc this is a 16-bit crc code used in both the mobitex da ta block and short data block. in transmit it is calculated by the modem from the data block bytes using the following generator polynomial: g(x) = x 16 + x 12 + x 5 + 1 i.e. crc from ccitt x.25. this code detects all (single) error bursts of up to 16 bits in length and about 99.998% of all other error patterns. the crc register is initialised to all ?1s? and the crc is calculated octet by octet starting with the least significant bit of ?byte 0?. the crc calculated is bit-wise inverted and appended to the data bytes with the most significant bit transmitted earliest. in receive mode, a 16-bit crc code is generated from t he data bytes of each mobitex data block or short data block as above and the bit-wise inverted value is compared with the received crc bytes. if a mis- match is present, then an error has been detected. 6.2.2 fec in transmit mode, during t7h, tsd and tdb, the modem generates a 4-bit forward error correction code for each coded byte. the fec is defined by the following h matrix: 7______0 3___0 11101100 1000 h = 11010011 0100 10111010 0010 01110101 0001
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 61 d/990/6 generation of the fec consists of l ogically anding the byte to be transmitted with bits 7 to 0 of each row of the h matrix. even parity is generated for each of t he 4 results and these 4 parity bits, in the positions indicated by the last 4 columns of the h matrix, form the fec code. in checking the fec, the received 12-bit word is logically anded with each row of the h matrix (earliest bit received compared with the first column). agai n even parity is generated for the 4 resulting words and these parity bits form a 4-bit nibble. if this nibbl e is all zero then no errors have been detected. other results ?point? to the bit in error or indi cate that uncorrectable errors have occurred. this code can correct any single error that has occu rred in each 12-bit (8 data + 4 fec) section of the message. example: if the byte to be coded is ?00101100? then the fec is derived as follows: h matrix row: 1 2 3 4 a 11101100 11010011 10111010 01110101 b 00101100 00101100 00101100 00101100 a and b 00101100 00000000 00101000 00100100 even parity: 1 0 0 0 where a is bits 7 - 0 of one row of the h matrix and b is the byte to be coded. the even parity bits apply to the result of ?a and b?. so the word formed will be: ?00101100 1000? sent left to right when the same process is carried out on these 12 bits as above, using all 12 bits of each h matrix row, the resulting 4 parity bits will be ?0000?. 6.2.3 interleaving all the bits of transmitted mobitex data blocks and short data blocks are interleaved by the modem to give protection against noise bursts and short fades. interleaving is not performed on any bits in the mobitex frame head. in the mobitex data block case, considering the 240 bits to be numbered sequentially before interleaving as 0 to 239 (?0? = bit 7 of byte 0, ?11? = bit 0 of fe c for byte 0, ... , ?239? = bit 0 of fec for byte 19 - see figure 15), then they will be transmitted as shown in figure 26. the mobitex short data block is interleaved in a similar way; referring to figur e 15 consider bytes 4 and 5 as the crc data and ignore bits 72 to 239 in the lower part of the diagram. i.e. the last bit to be transmitted will be ?71?. the modem performs the inverse operation (de-inte rleaving) in receive mode on both mobitex data blocks and short data blocks.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 62 d/990/6 figure 26 interleaving - input/output 6.2.4 scrambling all formatted bits of both mobitex data blocks and shor t data blocks are xored with the output of a 9-bit scrambler. this scrambler is initialised at the beginni ng of the first data block in every frame. the 511- bit sequence is generated with a 9-bit shift register with the output of the 5th and 9th stages xor?ed and fed back to the input of the first stage. the scrambl er is disabled during all other tasks, apart for tso.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 63 d/990/6 6.3 modem application examples 6.3.1 transmit frame example if the device is required to send a mobitex fram e the following control signals and data should be issued to the modem, assuming the device is not starting from a powersave state, txrxn is set to ?1? and that the relevant control bits have been set as r equired after power was applied to the device: 1. 6 bytes forming the frame head are loaded into the data buffer, followed by a 2-bit pause to let the filter stabilise, followed by setting t7h task. 2. device interrupts host c with irqn when the 6th byte is read from the data buffer. 3. status register is read and 18 bytes are loaded, followed by setting tdb task. 4. device interrupts host c with irqn w hen 18th byte is read from the data buffer. 5. status 1 register is read, host ma y load data and set next task as required: goto ?1? if the last data block for this frame has been transmitted and another frame is to be immediately transmitted goto ?3? if another data block in this frame is to be transmitted goto ?6? if no more data is to be immediately sent 6. 1 byte representing the ?hang byte? is loaded into the data buffer, followed by setting the tsb task. if the ?hang byte? has been transmitted and no more data is to be sent then a new task need not be written and the c can wait for the ibempty interrupt when, after a few bits to allow for the tx filter delay, it can shut down the tx rf circuits. a top level flowchart of the transmi t process is shown in figure 27. hang byte the filtering required to reduce the transmitted bandwidth causes energy from each bit of information to be smeared across 3 bit times. to ensure that the last bit transmitted is received correctly it is necessary to add an 8-bit ?hang byte? to the end of each message. thus the tasks required to transmit an isolated mobitex frame are: t7h + (n x tdb) + tsb when receiving this data, the extra byte can be ignored as its only function is to ensure integrity of the last bit and not to carry any information itself. it is suggested that a ?00110011? or ?11001100? pattern is used for this ?hang byte?.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 64 d/990/6 figure 27 transmit process
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 65 d/990/6 6.3.2 receive frame example if the device is required to decode a mobitex frame the following control signals should be issued to the modem. the host should set the control register and activate the acquire i q offset each time a new channel is selected. when the rssi indicates a valid signal or carrier only is present the acquire afc process should be activated (if required) before packets are decoded. this also assumes that the device is initially not in powersave, the correct fram e sync bytes have been loaded, the scren is set as required, txrxn bit is set to ?0? and a packet detect event has occurred, or a frame head is imminently expected: 1. 2 bits after a carrier has been detected or a frame head is expected the acquire bit clock bit is set to initiate the bit clock extraction sequence. 2. wait 12 bits and set sfh task to search for a mobitex frame head 3. device will interrupt host c with irqn when valid frame sync is detected and header bytes decoded. 4. host c reads status 1 register, c hecks moban and crcfec bit and reads out 2 frame head control bytes. 5. host c disables packet detect and sets the task to rdb to receive a mobitex data block. 6. device will interrupt host c with irqn when the data block has been received and the crc has been calculated. 7. host c reads status 1 register, checks crc validity and reads 18 data block bytes. the data quality register can also be read to obtain the received s/n level. 8. host c sets task if more information is expected: goto ?2? if last data block and another frame head imminently expected. goto ?5? if another mobitex data block expected. if the last data block has been decoded and no more in formation is expected then the task bits need not be set as the device will automatic ally select the idle state. a top level flowchart of the rece ive process is shown in figure 28.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 66 d/990/6 figure 28 receive process
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 67 d/990/6 6.4 transmitter the transmitter architecture allows constant envelope phase/frequency modulation, typically gmsk or gfsk. the transmitter uses an offset phase locked l oop (o-pll) to generate the transmitted signal. this has the advantage of very low spurious output minimising the need for spurious response filtering, thus reducing the overall cost of the radio and maximising power efficiency due to reduced losses. a description of the o-pll is given in sections 5.2 and 5.2.1. details of control of the transmitter are given in sect ion 5.3. a particularly important section for transmitter operation is section 5.3.11 where a number of t he transmitter control features are explained. the following sections will now review a number of design consideration when developing a rf design using the cmx990. 6.4.1 transmitter o-pll frequency tuning range considerations the o-pll system is a phased locked loop so one aspec t that needs to be considered in any design is the lock range, i.e. the band of frequencies over wh ich the loop will correctly lock to the desired frequency. there are a number of options available in using t he transmitter section and there are some constraints to the choices that need to be considered: transmit band required selection of the intermediate frequency (if) selection of high side or low side mixing selection of forward path ?modulation? filter frequency selection of feedback path filter frequency the transmit band is the range of frequencies over which the transmitter must be switchable. it is useful to define the highest required frequency as rfmax and the lowest required frequency as rfmin. the if selection and the choice of high side (lo>rf) or low side (lo gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 68 d/990/6 ? for low side mixing the minimum frequency to reject is 2lomin - rfmin ? for high-side mixing the minimum frequency to reject is rfmin there are two choices of filter with guaranteed pass bands of 83mhz and 118mhz and with adequate stop bands above 300mhz and 425mhz respectively. it is necessary to select the filter to ensure the lowest unwanted frequency is rejected i.e. above the stat ed stop band value. (for detail of how to select the desired filter see section 5.3.11). 6.4.1.2 vco range during the settling of the loop the vco will produce fr equencies that are different from the desired final value. mixing an undesired vco output frequency with the lo produces an if which can be some way off from the required if. this can result in the loop failing to converge for one of two reasons. firstly, if the if is sufficiently high that it is filtered by t he feedback path filter; this e ssentially removes the feedback path and makes the feedback signal appear as a zero frequency (when it is in fact high). if this is allowed to happen the loop will drive the vco away from t he desired frequency rather than towards it. this means that the vco must not be allowed to pr oduce frequencies that cause the if to exceed the minimum filter pass band value. this constrains the tx vco frequency prior to enabling tx offset pll (vcoout) such that: vcoout max < lomin + ffilter for low-side mixing (ffilter is 83mhz or 118mhz) vcoout max must be in excess of the required rfmax if the frequency band is to be achieved or vcoout min > lomax ? ffilter for high-side mixing (ffilter is 83mhz or 118mhz) vcoout min must be below the required rfmin if the frequency band is to be achieved secondly, the loop may fail to converge if the rf signal from the vco is allowed to move too far on the other side of the required frequency. in this region it is possible to produce an if from the rf image frequency. as the rf frequency gets close to the lo value the if approaches zero. as the if is ac coupled internally, this may allow the subsequent limiter to self-oscillate and the loop may fail to converge. this constraint to the vco is such that: vcoout min > lomax for low-side mixing vcoout min must be below the required rfmin if the frequency band is to be achieved or vcoout max < lomin for high-side mixing vcoout max must be in excess of the required rfmax if the frequency band is to be achieved all these conditions should ideally to be met for t he loop to be guaranteed to converge correctly however the filters are not ?brick wall? so some operation beyond these limits is possible. further the issue with a zero if, noted above, will not necessarily cause a problem as the time constant of loop filter will usually mean that the vco will transition through the zero point and continue to lock correctly. the operation of these limits is shown in figure 29. the upper diagram shows the frequency plan for the architecture of figure 17. in this case high-side mix is used so the conditions given above are applied resulting in the conclusion that the minimum fr equency the vco can achieve should be in the range 796 ? 819mhz and the maximum frequency the vco can achi eve should be in the range 824mhz to 909mhz. these become constraints on the vco design e.g. the vco with v tune =0v should be in the 796-819mhz range and with v tune =v dd should be in the range 824 to 909mhz. also note that due allowance for tolerances and production variations should be made.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 69 d/990/6 rfmin rfmax lomax lomin 824mhz 819mhz 909mhz 914mhz lomax - ffilter 796mhz range of vcomax range of vcomin rfmin rfmax lomax lomin 850mhz 800mhz 890mhz 940mhz lomax - ffilter 822mhz range of vcomax range of vcomin ??? figure 29 allowed vco ranges considering now the lower diagram in figure 29, here the required tuning band is 800mhz to 850mhz. in this case the lomax ? ffilter comes above rfmi n so it appears no vcomin range is available for successful operation. clearly vcomin must be below rfmin so the risk is the loop will not lock because the if filter has removed the feedback signal. the solu tion is to use the pre-change facility of the cmx990 were the vco loop filter can be pr e-conditioned under user control to v dd vco/2 using the ?tx vco charge bit (see section 5.3.11). provided that the fr equency that results from this is within the range 822mhz to 890mhz the loop will converge to the correct values.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 70 d/990/6 6.4.2 start up the timing of the turn-on of the transmitter needs careful control. a typical sequence is shown in figure 30. the first step is to program the if and rf synthesisers to the correct frequencies for the desired transmitter channel. when time has been allowed for the pll?s to lock the transmitter circuits (excluding the pa) should be enabled. in order for the o-pll to function it is necessary to: ? enable the tx dac (bit 0 of register $03) ? enable tx mode (bit 5 of register $03) this is because otherwise the input to the i/q modulator is in a quiescent state with the result that the modulator does not produce significant output. as a re sult there is no reference signal for the o-pll and hence it will not lock. depending on the leakage through the pa the o-pll s hould start to lock up. the limiter has been designed to allow locking at low input levels so the loop will start to lock with a signal level of around -50dbm at the o-pll mixer input (w ith 0db attenuation). if leakage levels through the pa are particularly low it may be necessary to provide a small amount of bi as (e.g. dac0 control) to increase leakage to start locking. typical levels are shown in table 1. pa ?off? pa ?on? level at output of stage feedback path antenna output feedback path antenna output pa output -23dbm +31.2dbm coupler -45dbm -23.5dbm +9.2dbm +30.7dbm tx rx switch -43.5dbm +30dbm attenuator -48dbm +6.2dbm cmx990 attenuator -48dbm (1) -4.8dbm (2) notes: (1) cmx990 attenuator setting: 0db (2) cmx990 attenuator setting: ?10db table 1 example tx loop levels bit 4 in register $24 enables the pre-conditioning si gnal to the charge pump output txpll (see section 5.3.11). this will charge the loop filter components to v dd vco/2 through a resistive divider network of 10k (note this is not shown in figure 30). with typical loop filter values this will charge the loop filter in less than 5ms, however the user may control the amount of pre-charge by varying the time the pre-charge is enabled. the user should ensure that the pre-char ge circuit is disabled when they wish locking of the transmitter offset pll to commence. it should be not ed that following enabling the txrfif bit (register $04, bit 0) there is a delay while data is clocked thr ough the tx dac and filters. during this time the loop may not exhibit anticipated lock behaviour as the phas e detector reference input has little or no signal.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 71 d/990/6 main pll aux pll tx/rx bit & tx dac enable txif pll enable programming data tx enable rx / tx switch tx pll vco control line pa ramp control line (dac 0) dac 0 ramping data / t7h / tdb (as required etc.) regulator turn on delay regulator turn on delay o-pll lock time pa ramping time synthesiser lock time tx output power (e.g +30dbm) -36dbm transmit power vs. time response tx attenuator =10db figure 30 tx timing diagram (not to scale) the time required for the o-pll to lock will depend on a number of factors including the loop filter design. as a guideline typical lock-times are around 100-200s. when observing lock time a number of factors
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 72 d/990/6 need considering, not just the generic lock time of the loop. most important are the stability of the local oscillator sources. pulling or pushing of the vco dur ing the pll locking can cause a transient response in the pll and typically this is much longer than that of the o-pll. a buffer between vco and cmx990 lo input is recommended to minimise this effect. another concern is power ramping. during this stage it is common that power supply transients will cause some pushing of the vco. furthermore, changes in impendence presented by the pa can cause pulling. these effects require the o-pll to respond and stabilise the frequency (note: this is very much the same problem with traditional two-point fm vco modulati on). the effect is demonstrated in figure 31 where the pa is ramped rapidly to full power and is a wo rst case test as no buffering is provided between pa and vco; the transient in this case has decayed wi thin about 8 symbols of 8kbit/s data (i.e. 1ms). controlled power ramping can be used to optimise performance. hz ref lv l 30 db m ref lv l 30 db m 30.4 db offs c f 822 mh sr 8 k meas sign a frequen c demod 2 f fre q t 1 a ln trg 0 19.75 symbols -5 k 5 k 1 marker 1 [t1] 4.00 sym freqdev 454.212 hz 1 [t1] 4.00 sym freqdev 454.212 hz burst not found date: 5.oct.2006 09:06:26 figure 31 tx loop transient caused by increasing pa output power from ?10dbm to +30dbm; 90mhz if, f tx = 822mhz, external lo at the end of a transmission, the various stages shoul d be disabled / switched in reverse sequence to that shown in figure 30. 6.4.3 spurious emissions the low level and small number of spurious emissi ons from the o-pll transmitter are a major advantage of the technique. the major source of spurious si gnals is the power amplifier harmonics. the level of these will be set by the selected pa and a harmonic filt er must be provided to remove these. the only significant spurious signals generated by the o-pll trans mitter is lo leakage from the offset mixer to the rf input port. the cmx990 mixer has been designed to have low local oscillator leakage meeting the typical requirements (e.g. -36dbm in europe, -17dbm in usa). performance is optimised by taking the o- pll feedback signal from the pa output, thus am plification of the lo spurs is avoided.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 73 d/990/6 the o-pll loop can generate some spurs within the loop bandwidth. these spurs are generated by harmonics of lo signals and mixing products. as a result some care with frequency plans is required, for example operation on harmonics of the txif is problem atic (e.g. 450mhz tx with a 45mhz txif). these frequencies can be avoided by selecting a suitable if that avoids such problems. for systems with a wide tuning range it may be necessary to use a slightly di fferent if for some frequencies, e.g a 46mhz if for frequencies close to 450mhz. 6.4.4 variable bt the cmx990 offers the ability to select the bt fa ctor in the transmit modulation. this allows characteristics to be optimised for a particular bit/rat e channel bandwidth. options of bt = 0.27, bt = 0.3 and bt = 0.5 are available (see section 5.3.8.2). figure 32, figure 33 and figure 34 show the effect of changing bt. a unit d b m r b w 2 0 0 h z swt 4.2 s v b w 2 k h z r e f l v l 5 d b m r e f l v l 5 d b m r f a t t 3 0 d b 3 . 3 5 k h z / c e n t e r 8 0 0 . 0 0 1 6 2 3 8 m h z s p a n 3 3 . 5 k h z 1 r m 2 r m 1 v i e w 2 v i e w 2 v i e w 2 r m - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 - 9 5 5 inner trace is cmx990 with bt = 0.3 outer trace is cmx990 with bt = 0.5 figure 32 modulation spectrum of cmx990 at 8kbps with different bt for bt=0.27 see figure 37
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 74 d/990/6 r e f l v l 5 d b m 5 d b m r e f l v l 5 d b m 5 d b m a 0 8 s y m b o l s c f 8 0 0 . 0 0 1 6 2 4 m h z s r 8 k h z m e a s s i g n a l e y e [ i ] d e m o d 2 f s k r e a l t 1 - 2 5 0 m 2 5 0 m figure 33 cmx990 modulation eye diagram at 8kbps with bt = 0.3 (measurement filter bt=1) r e f l v l 5 d b m 5 d b m r e f l v l 5 d b m 5 d b m a 0 8 s y m b o l s c f 8 0 0 . 0 0 1 6 2 4 m h z s r 8 k h z m e a s s i g n a l e y e [ i ] d e m o d 2 f s k r e a l t 1 - 2 5 0 m 2 5 0 m figure 34 cmx990 modulation eye diagram at 8kbps with bt = 0.5 (measurement filter bt=1)
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 75 d/990/6 6.4.5 transmitter performance the modulation of the cmx990 is produced digita lly, ensuring excellent accuracy and no need for alignment of deviation as might be required wi th an analogue modulator. the cmx990 is designed to meet the requirements of various internati onal standards including en 300 113 and en 300 220 in europe and 47 cfr 2.1049 & 90.210 (j) applicable in the usa (figure 35). ref lvl 0 dbm ref lvl 0 dbm rf att 30 db a unit dbm 1m a center 800.001496 mhz span 50 khz 5 khz/ rbw 300 hz swt 2.8 s vbw 3 khz -90 -80 -70 -60 -50 -40 -30 -20 -10 -100 0 limit check : passed fcc210j date: 31.mar.2004 14:22:00 figure 35 modulation from cmx990 with 47 cfr 90.210 (j) emission mask 6.4.5.1 adjacent channel power the en 300 113 requirements are the most demanding limits of those listed above, requiring -60db adjacent channel power for 12.5khz channelled syst ems and -70db adjacent channel power for 25khz channelled systems. these requirements can be met by the cmx990. performanc e with a 25khz system at 9600bps is shown in figure 36. for 12.5khz channels a data rate of 8kbps per sec ond is required for some standards with a nominal bt=0.3. generating this modulation in an ideal case from a signal generator and measuring the adjacent channel power (acp) using the measurement bandwid th specified in en 300 113 annex b.1 suggests that meeting the ?60db limit is a significant chall enge (see table 2). for this reason a bt option of 0.27 has been included and using this setting the cmx990 achi eves -62 or -63db adjacent channel power (see
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 76 d/990/6 figure 37). interestingly, during development, tests were made with reduced deviation while maintaining a bt=0.3 during which it was found necessary to reduc e the deviation substantia lly before the 60db limit could be achieved. it was therefore concluded that the tighter filter (reduced bt) was the preferred option. ref l v l 30 d b m ref l v l 30 d b m a l n l n 3 0 . 4 d b o f f s e t 1 a v g c e n t e r 8 6 7 m h z s p a n 1 0 0 k h z rbw 500 hz vbw 500 hz swt 2 s mixer -2 0 d b m unit d b m 1 0 k h z / rf att 1 0 d b 1 s a - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 1 0 2 0 - 7 0 3 0 1 m a r k er 1 [t1] 17.36 dbm 867.00030060 mhz 1 [ t 1 ] 1 7 . 3 6 d b m 867.00030060 m h z ch pwr 27.40 d b m acp up -71.40 d b a c p l o w - 7 1 . 2 7 d b cu1 c u 1 c l 1 cl1 c 0 c 0 figure 36 9.6kbps spectrum, 25khz, +30dbm, bt=0.5 bt product adjacent channel power (dbc) 0.25 -68 0.27 -63 0.28 -62 0.29 -61 0.30 -59 0.31 -57.5 0.32 -56.5 table 2 acp for 12.5khz channel versus bt product for digital signal generator (8kbps)
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 77 d/990/6 a l n l n u n i t d b m m i x e r - 2 0 d b m r b w 5 0 0 h z v b w 5 0 0 h z s w t 1 s 1 s a 3 0 . 5 d b o f f s e t r e f l v l 3 0 d b m r e f l v l 3 0 d b m r f a t t 1 0 d b 5 k h z / c e n t e r 4 5 4 . 1 m h z s p a n 5 0 k h z e x t 1 a v g - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 1 0 2 0 - 7 0 3 0 1 m a r k e r 1 [ t 1 ] - 6 2 . 2 3 d b m 4 5 4 . 0 7 5 0 0 0 0 0 m h z 1 [ t 1 ] - 6 2 . 2 3 d b m 4 5 4 . 0 7 5 0 0 0 0 0 m h z c h p w r 2 6 . 6 3 d b m a c p u p - 6 2 . 2 6 d b a c p l o w - 6 3 . 9 9 d b c u 1 c u 1 c l 1 c l 1 c 0 c 0 figure 37 tx acp of ?62dbc (12.5khz channel setti ngs) at +30dbm carrier, 8kbps, bt = 0.27, if 90mhz a further issue to note concerning the adjacent channel power is that phase noise from both the main and aux local oscillators contribute to the adjacent channel power. the phase noise of the two local oscillators should be well below the adjacent channel power that is being sought. note that a cw source which achieves ?60dbc adjacent channel will be much worse t han this when modulated. a further point to note is that phase noise is improved by the ac tion of the lo dividers in the cmx990. the phase noise of the vco in the o-pll is le ss significant when considering adjacent channel performance as the adjacent channel area is within the loop bandwidth. as a result the phase noise will reflect that of the reference source (aux lo) and any noise added in the feedback path (i.e. the main lo). 6.4.5.2 wideband noise wideband noise requirements vary between products and depending on particular international standards. a good guideline is cept/erc/rec/74.01 wh ich is based on itu sm.329. this mask is required by en 300 113 for example. as will be seem from figure 38 the cmx990 comfortably meets the requirements for a 2w (+33dbm) transmitter.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 78 d/990/6 a l n u n i t d b m m i x e r - 2 0 d b m r e f l v l - 1 0 d b m r e f l v l - 1 0 d b m r f a t t 1 0 d b c e n t e r 8 6 7 m h z s p a n 1 m h z 1 0 0 k h z / r b w 1 k h z v b w 1 k h z s w t 2 . 5 s l n 1 s a 1 a v g - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 1 0 - 1 0 1 1 d e l t a 1 [ t 1 n o i ] - 1 1 6 . 6 0 d b c / h z 2 0 0 . 4 0 0 8 0 1 6 0 k h z 1 [ t 1 ] - 1 1 6 . 6 0 d b c / h z 2 0 0 . 4 0 0 8 0 1 6 0 k h z 1 [ t 1 ] - 1 3 . 7 8 d b m 8 6 6 . 9 9 8 9 9 8 0 0 m h z f x d - 1 3 . 7 8 5 d b m f x d d a t e : 1 7 . o c t . 2 0 0 6 1 6 : 0 3 : 5 0 -119dbc/hz at +/-500khz figure 38 cmx990 wideband noise performance showing cept/erc/rec/ 74.01 emissions mask for a 2w (+33dbm) transmitter 6.5 receiver the design of the cmx990 is such as to allow rece iver requirements of the mobitex standard to be met. in addition the receiver is also capable of meeti ng the requirement of standards such as en 300 113 and en 300 220. 6.5.1 architecture overview the receiver architecture is based on the classi c superhetrodyne approach. the cmx990 provides the 1 st mixer and if stages with agc followed by conver sion to i/q format baseband signals. these are then converted to digital signals in sigma-delta converters , which also provide adjacent channel filtering, before demodulation.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 79 d/990/6 the first stage of the cmx990 receiver is a mixer intended to convert from rf to a 1 st intermediate frequency (if) of around 45mhz. the mixer is an image re ject type thus minimising the external filters required before the mixer. the mixer would normally be preceded by input transmit/receive switch, low noise amplifier and a filter. a typical cascaded noi se figure for these stages is around 4db with a recommended gain of around 10db. the noise figure of the mixers is very good for an image reject mixer circa 13db to 15db depending on configuration. this lo w noise performance allows the pre-gain required to achieve a reasonable overall noise figure to be minimised which has the benefit of making system intermodulation-performance better. it will be noted that the mixer is a gilbert cell type therefore requires a differential input. this can be achieved with a narrow-band lc circuit or a balun transformer (see section 4.5). the image reject network is selectable to permit high si de or low side local oscillator injection (see ?sign? bit in register $24). following the 1 st mixer the signal is passed off chip. a single ended output stage is used to ease connection to if filter components. the 1 st if can be in the range 44-46mhz with 45mhz being a typical choice. filtering is required at this point to ac hieve the typical performanc e requirements and the amount of selectivity can be tailored for a particular design. for example, mobitex adjacent channel filtering can be met with digital filters at baseband alone, however the blocking signal test at 84db puts severe demands on the dynamic range of the baseband sections so filtering at the if is necessary; a 2-pole crystal filter is all that is required in this case. en 300 113 has more severe adjacent channel requirements so reasonable adjacent channel selectivity at the 1 st if is recommended. a 4-pole crystal filter should be satisfactory. a summary of sugges ted filter requirements can be found in table 3. the output of the if filter should be connected to if in pin which goes into a gain controlled low noise amplifier stage. 45db of agc range is available in 15db steps. the output of the if amplifiers passes to i/q mixers which are fed a by a divide by 4 circuit from the if local oscillator. the mixers include dc offset compensation (see section 6.5.2). baseband amp lifiers are then used to provide the correct input level to the adc. the baseband amplifiers also incl ude 55db of rejection at 1.92mhz which is a typical adc image frequency. this combined with at least 40db of external rejection from the if filter provides adequate rejection to meet blocking requirements. please note that the adc image response frequency varies with the adc clock frequency. the image respons e has a fixed relationship to the clocks i.e. baseband clock divided by 10 (see figure 24); so for a 8kbit/s system the image response is at 1.92mhz but at 960khz for a 4kbit/s system. for multi-rate systems care is required to ensure the blocking / spurious response rejection perfo rmance is met under all conditions. frequency offset radio modem mode (2 pole filter recommended) en 300 113 mode (4 pole filter recommended) 12.5 khz 10db 30db 25 khz 15db 30db 50 khz 25db 50db 100 khz 25db 50db 1 mhz to 10 mhz 40db 50db pass band ( 3.5 khz) 3db typical 3db typical note: attenuation relative to the pass band (with the exception of the pass band specification) table 3 if filter requirements,12.5khz channel spacing the adc are sigma delta types providing high dy namic range and adjacent channel rejection (see figure 39). internal dc offset correction is provided to maximise the useable range. after the adc demodulation is provided along with rssi/agc algorithms. rssi is available from a register. agc can be controlled automatically or manually. the bas eband section also provides afc measurement. results are available to the host and can be used (via aux dac 1) to control an external reference oscillator.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 80 d/990/6 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.5 1.0 1.5 2.0 2.5 bit rate attenuation / db figure 39 baseband filter response scaled as a func tion of bit rate (e.g. for 8kbit/s 1.0 = 8khz) to design a complete receiver system using the cmx990 it is recommended that an analysis is made of receiver parameter such as overall noise figure, intermodulation performance etc. these factors need to be considered along with adjacent channel rejection, blocking and spurious responses discussed above. a typical gain, noise figure and intermodulation partiti on is shown in table 4 which assumes the filter performance specified in table 3. the partition us es suggested performance for external ?front end? stages. the calculated results show a noise figure of 8.3db. cmx990 stages switch & filter lna bpf 1 st mixer if filter agc/iq digital filter output stage specifications: gain (db) -1.8 15.0 -3.0 -1.4 -3.0 63.0 0.0 0.0 nf (db) 1.8 1.2 3.0 15.0 3.0 8.5 0.0 0.0 i/p ip (dbm) 40.0 0.0 40.0 9.5 40.0 -44.0 99.0 99.0 i/p cp (dbm) 30.0 -10.0 30.0 -7.0 30.0 -54.0 99.0 99.0 cumulative response: pregain (db) 0.0 -1.8 13.2 10.2 8.8 5.8 68.8 68.8 cum nf (db) 8.3 6.5 20.0 17.0 11.5 8.5 0.0 0.0 i/p te (%) 9.0 8.5 0.8 51.3 2.3 28.1 0.0 0.0 cum ip (dbm) -1.3 -3.1 12.5 9.5 33.9 -44.0 97.5 99.0 i/p im (%) 0.0 24.0 0.0 76.0 0.0 0.0 0.0 0.0 table 4 typical gain / noise figure / intermodulation partition for cmx990 considering the detail of table 4 the ?ip te (%)? is the percentage of the overall receiver noise figure, calculated as a noise temperature, contributed by eac h stage. it will be seen that the largest contribution comes from the 1 st mixer (51.3%). to improve sensitivity therefore increasing the gain before the 1 st mixer will be very effective in reducing the overall receiv er noise figure. such a change will have a significant effect on the intermodulation performance however as the ?i/p im (%)? s hows that 76% of the intermodulation in the system is coming from the 1 st mixer stage. the ?cum ip (dbm)? is the third-order intercept point calculated for the input of each stage in cluding the effect of all the following stages, so the
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 81 d/990/6 value in the ?switch & filter? column would be the val ue observed looking into the receiver; the value in the ?1 st mixer? column would be that measured look ing into the cmx990. note these values and calculations are only valid for the design based on the stage specifications given in table 4 however they should give a useful indication of key areas that control the performance of the overall system. input level (dbm) ber % -107 0 -110 0.005 -113 0.16 -115 0.525 -116 0.98 -117 1.365 table 5 sensitivity results for cmx990 system (8kbps) 6.5.1.1 frequency planning frequency planning for the cmx990 is a complex issue as requirements of both transmitter and receiver must be considered. the choice of ifs is limited however and this tends to reduce the options to a manageable number. a typical frequency plan is show n in figure 17 and some further typical configurations in table 6. rx band (mhz) tx band (mhz) rx if sign rx lo (mhz) tx if if div tx lo (mhz) lo range bottom top bottom top (mhz) bit rx bo ttom top (mhz) setng bottom top (mhz) 935 941 896 902 45 high 1960 1972 84 /2 1960 1972 12 864 870 819 825 45 high 1818 1830 90 /2 1818 1830 12 850 864 814 819 45 high 1790 1818 81-90 /2 1790 1818 28 426.6 429.5 416.6 419.5 45 low 763.2 769 40 /4 753.2 759 15.8 453.1 453.4 459.6 459.9 45 high 996. 2 996.8 40 /4 999.2 999.8 3.6 table 6 possible frequency plan for cmx990 in some common frequency bands some points to consider when choosing frequencies are: ? 45mhz tx/rx offset: with a a 45mhz tx/rx offset transmi t and receiver operation can be achieved without needing to re-tune the main local oscillator by using a 90mhz tx if (as shown in figure 17). ? pll lock range: it is often advisable to minimise main pll tuning range (see section 6.5.1.2). one way of do this is to adjust the frequency of the if pll between tx and rx (as suggested in table 6). the if pll is usually less critical in terms of phase noise and can have a relatively high comparison frequency (e.g. 100khz compared to 12.5khz for t he main pll) making lock time and spurious performance easier to achieve. ? tx spurs: the o-pll transmitter will generate spurs close to harmonics of it?s if, for example if 45mhz tx if is used operation close to 450mhz should be avoided. ? rx spurious responses: like all receivers the cmx990 will hav e some spurious responses, the most obvious being the image response but also half if re sponse, higher order lo / if products etc. the designer must take care to evaluate and test re sponses for a particular frequency plan. one response that the cmx990 architecture avoids is the 2 nd image response due to the use of ?zero if? in the second conversion. ? the receiver if: the image reject mixer works best at 45mhz however due to spurious responses it is sometimes necessary to move this. keeping the if as close a possible to 45mhz is recommended. (note: in some areas tv carriers on 45mhz c an be problematic, in these areas a move to 45.0125mhz if has proved sufficient to avoid the interference).
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 82 d/990/6 6.5.1.2 phase noise like all radio designs the phase noise of the local osc illators plays an important ro le in the overall system performance with a cmx990 design. in order for t he receiver to meet adjacent channel rejection requirements, the phase noise of the local oscillato r in the adjacent channel must be better that the rejection requirement, by a reasonable margin, otherwise the process of reciprocal mixing will limit overall performance. the same process applies to spurious response rejection and blocking. one factor to consider when calculating phase noise is the cmx990 main lo is divided by two prior to the mixer. this will provide a theoretical 6db improvem ent in phase noise (the improvement in practice is close to this figure, typically in the range 5-6db). the phase noise requirements for the aux lo are generally less stringent as the 1 st if filter provides protection. for a thorough receiver design a detailed partition of filtering requirements and phase noise is recommended, an example of which is shown in table 7. a full explanation of this is beyond the scope of this datasheet however note that from the highlight ed numbers the other values can be calculated. the effect of phase noise is observed by the fact the actual selectivity is much less than the amount of filtering provided in the receiver ? the if filter provided 30db and the baseband 48db (78db total) however the signal to noise margin with a +60db interferer (- 47dbm to ?107dbm) is only 0.8db. using this calculation method we find that with the given lo phase noises, the adjacent channel rejection would be just over 62db. this could be degraded further if intermodulati on in the if stages contributes to the total interference power. some additional margin has been allowed as the target s/n is quoted as 12db wereas the actual limit of 1% ber is 11.5db (section 6.5.5). specification limit -47.0 dbm wanted signal level -107.0 dbm target s/n 12.0 db normal s/n 17.0 db noise bandwidth 8000.0 khz thermal noise -124.0 dbm relative atteuatiuon requirement -72.0 db selectivity at rf input -78.0 db rf filter relative attenuation 0.0 db selectivity at mixer #1 input -78.0 db lo1 phase noise margin 6 db lo1 sideband noise ratio -78.0 db lo1 ssb phase noise density -117.0 dbc/hz total noise at output of mixer #1 -121.5 dbm selectivity at 1st if input -78.0 db s/n at mixer #1 output 14.5 db 1st if filter selectivity -30.0 db selectivity at mixer #2 input -48.0 db lo2 phase noise margin 20 db lo2 sideband noise ratio -62.0 db
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 83 d/990/6 lo2 ssb phase noise density -101.0 dbc/hz selectivity at 2nd if input -48.0 db total noise at output of mixer #2 -121.4 dbm total interference at output of mixer #2 -125.0 dbm s/n at mixer #2 output 12.8 db 2nd if selectivity 0.0 db baseband digital filter attenuation -48.0 db s/n margin 0.8 db table 7 example phase noise partition 6.5.2 dc calibration the signal levels in the receiver are small, typically only a few mv at sensitivity. for the demodulator algorithms to work correctly the dc offset must be r educed well below the level of the signal. to do this the cmx990 has two stages of dc correction. the first stage allows an analogue correction to be applied prior to the adc (see figure 40), the offset val ue being controlled from registers $18 and $19 (section 5.3.7). this allows the analogue signals prior to the a dc stage to have an error of less than 0.5mv. this maximises the dynamic range available from the adc. the second element of dc offset correction is based on averaging the received signal. this is done as part of the demodulator section and the correction is applied by adding/subtracting the measured dc offset to the received data samples. dc offsets can be corrected by turning off the ?front end? circuitry (figure 40) and measuring the remaining signal then applying an appropriate correction. this process can be carried out automatically by the cmx990 via the command register ($01, bit 6). an output control signal is provided from the chip to enable/disable the external lna with appropriate timi ng. the disabling of the ?front end? is beneficial as it should ensure that no signal is present while dc offs ets are being estimated. this is crucial in allowing a fast estimate of offsets as if signal is pr esent the modulation can not be guaranteed not to have dc content, furthermore large signals introduce large potent ial errors when trying to estimate a precise dc value. by contrast noise, if measured over a suitabl e period, will have a mean value very close to the dc offset value. the result of any measurement of noi se will vary somewhat: a longer measurement time will improve the accuracy. the cmx 990 algorithm has been selected to give a good combination of speed and accuracy for typical bit rates. the automatic sequence is shown in section 5.3.4.3 (repeated below). during the ?tracking? phase a first measurement of the error is taken and correction applied to the hardware ?coarse correction? registers. with this co rrection applied the fine correction is measured. after 25 bits the receiver ?front end? is enabled and the re sults of the calibration process are then used to correct the received signal prior to digital demodulation. ? reset (equivalent of reset task in command register) ? turn off receiver ?front end? ? run with tracking for 25 bits to correct i/q offset errors ? turn on receiver ?front end? and apply offset ? revert to normal setting (hold / fine / coarse) on completion of the automatic sequence it is recomm ended that either the ?fine? or ?hold? modes are used. the ?hold? mode uses the measured calibrati on and does not update. this might be appropriate if the received data has extremely long sequences of 1?s or 0?s. normally best results are achieved with the ?fine? tracking were the cmx990 will automatically measure and update the fine dc offset values. it should be noted that the algorithm used in ?fine? mode is intelligent and differentiates between signal and noise and applies an appropriate correction. the time constant of the algorithm is such that imbalanced data sequences should not effect the dc correction significantly.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 84 d/990/6 when using the ?coarse tracking? mode the values of the ?coarse offset? registers are updated automatically while this mode is enabled. the ?fine offset? values are not updated during this mode, the algorithm resuming from it?s last state when fine track is next enabled. if no offset correction is required the ?reset and ho ld? mode should be used. this will set the ?coarse? and ?fine? offsets to zero. the ?coarse dc offset? value can be read by the hos t and values can also be written by the host (see section 5.3.7) . this allows the host to ?remember? values for a particular hardware setting, for example a particular channel, which can then be written back to the cmx990 next time that setting is used. this allows operation on a channel without needing to run the full dc offset correction process. access to the ?fine? offset values is not currently supported. figure 40 dc offset correction scheme 6.5.3 matching typical matching arrangements are given in section 4. this section gives some additional information that might be helpful to designers. 6.5.3.1 if output typical impedance of the if output port is 290 ? j138 at 45mhz. a typical output match to 50 is shown in figure 41.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 85 d/990/6 cmx990 22pf 470nh ifout output (50 ) figure 41 mixer output (ifout) matching 6.5.3.2 if input typical impedance of the ifin port is approximately 4k in parallel with 3.5pf at 45mhz. for test purposes it is useful to match the ifin stages to 50 . this can be achieved with the match shown in figure 42 if input matching ch1 s 11 1 u fs cor del prm ch2 s 11 log mag ref 0 db 10 db/ start 35.000 000 mhz stop 55.000 000 mhz cor del prm marker 1 45 mhz 20 sep 2006 10:35:23 1 2 3 1_ 46.084 1.7773 6.2861 nh 45.000 000 mhz 2_ 36.633 -183.47 35 mhz 3_ 56.836 215.75 55 mhz 1 2 3 1_:-26.986 db 45.000 000 mhz 2_:-.8511 db 35 mhz 3_:-.9486 db 55 mhz figure 42 if input matching 6.5.4 rx mixer options the receive mixer in the cmx990 is an image reject ty pe allowing a reduction in external filtering thus allowing a minimum cost solution. certain radio modem products may require better inter-modulation performance than can be achieved with the image reject ar chitecture. in this case an external mixer is cmx990 2.7pf 1.5 h ifin input (50 )
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 86 d/990/6 recommended and to simplify external circuits the cmx 990 incorporates a bypass switch for the transmit loop local oscillator divide-by-2. this allows the cmx990 transmit local oscillator to be re-used in an external mixer. when an external mixer is used, the power consumption can be reduced by disabling the circuits controlled by the rxf1 and rxf2 bits in the power up 1 register ($04). a typical configuration is shown in figure 43. in this mode the main lo and the tx frequency are rela tively close. careful attention in the pcb design should be paid to isolation between lo and tx sections to avoid interference between the two sections. figure 43 block diagram of cmx990 show ing use of external receive mixer
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 87 d/990/6 6.5.5 signal to noise the performance of the receiver is based on the signal to noise performance of the demodulator. this achieves a bit error rate of 1 in 100 at 11.5db si gnal-to-noise. performance is shown in figure 44 which also shows performance degrades a little with the addition of a crystal if filter (dashed line). 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 10 11 12 13 14 15 signal to noise / db ber / % figure 44 ber vs signal-to-noise for cmx990 with and without an if filter 6.5.6 dynamic range, rssi and agc the cmx990 has a built in agc algorithm. progra mmable gain has 4 steps of 15db (i.e -5db, +10db, +25db and +40db). it is beneficial to allow as lar ge an operating window as possible as the agc has a certain amount of hysteresis allowing the signal to rise more than 15db before the gain is backed off. the cmx990 measures the signal level in baseband. this information is used to control the agc but is also available via the control interface. if agc is being controlled by the host rssi need to be correct as described in section 5.3.7. if agc is being control by the cmx990 the value of the rssi value reported is automatically corrected for the agc value in use at the time. detail descriptions of the operation of the rssi are given in sections 5.3.12.2 and 5.3.8.6. 6.5.6.1 dynamic range the dynamic range of the receiver must be partitioned bet ween various requirements. key to this is the dynamic range of the adc within ic that converts the i/q signals into the digital domain. these converters have a dynamic range of at least 85db. this must be partitioned between various factor such as filtering headroom, signal noise, quantisation noise margin etc. leaving an operating window. the proposed partition is shown in figure 45. other partitions are possible depending on adjacent channel requirements, external filter ing, external gains etc.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 88 d/990/6 figure 45 adc input dynamic range partition 6.5.6.2 listen before talk a number of radio system use ?listen before talk? (lbt) operation, for example this is specifically referenced in en 300 220. although lbt algorithms may take many forms en 300 220 specifies specific listening periods and requirements. the minimum lis tening time is 5ms however the default averaging time for rssi on the cmx990 is much longer than this (64ms). the averaging time can be reduced to 0.5ms (see section 5.3.8.6) which is convenient as the random part of the listing time if the channel is occupied, should be in 0.5ms steps. 6.5.7 signal processing the cmx990 includes the demodulation functions, these are implemented digitally. algorithms are consistent with mobitex mobile burst timing struct ure and requirements. the received waveform can be inverted to allow high side or low side mixing in the re ceiver (see section 5.3.4.4, note this is separate and additional to the facility to invert the operation of the im age reject mixer in the receiver section 5.3.9) it will be noted that when powered up, the cmx990 needs to acquire base channel. the baseband has been optimised to achieve this while also giving mi nimum power consumption in normal operation (i.e. maximum sleep times).
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 89 d/990/6 7 performance specification 7.1 electrical performance 7.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. unit supply (v ddh - v ssh and v ddvco - v ssh only) -0.3 4.0 v supply (all other v dd - v ss ) -0.3 3.0 v voltage on any pin to v ssh -0.3 v dd + 0.3 v current into or out of any v dd or v ss pin -100 +100 ma current into or out of any other pin -20 +20 ma voltage between any two v ss pins -0.3 +0.3 v voltage between any two v dd pins (except v ddh ) -0.3 +0.3 v q1 package min. max. unit total allowable power dissipation at t amb = 25 c ? 3500 mw ... derating above 70 c ? 35.0 mw/c storage temperature -55 +125 c operating temperature -40 +85 c 7.1.2 operating limits correct operation of the device outsi de these limits is not implied. notes min. max. units supply (v ddh - v ssh ) 3.0 3.6 v supply (v ddvco - v ssh ) 3.0 3.6 v supply (all other v dd - v ssh ) 2.25 2.75 v voltage difference between supplies: v ddh to v ddvco 0 0.2 v between all other v dd 0 0.2 v all v ss to v ssh 0 50 mv operating temperature -40 +85 c clock frequency 1 3.8 24 mhz bit rate 1 4000 16000 bits/sec notes: 1 error in rf and if frequencies and bit rate is directly related to the clock frequency.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 90 d/990/6 7.1.3 operating characteristics for the following conditions unless otherwise specified: clock frequency = 19.2mhz, bit rate = 8k bits/sec, noise bandwidth = bit rate, v ddh = v ddvco = 3.0v to 3.6v, all other supplies 2.25v to 2.75v, t amb = -40c to +85c. notes min. typ. max. unit dc parameters i dd (powersaved) at v ddh = 3.3v 2 ? 50 200 a total tx i dd (v ddh = 3.3v) 2,9 ? 137 ? ma total rx i dd (v ddh = 3.3v) 2,9 ? 148 ? ma individual supply currents: v dd vco (synths in lock, rx mode) 2,7 ? 1 ? ma v dd vco (synths and tx loop in lock) 2,8 ? 24 ? ma v dd ana (in rx mode) 2 ? 8 ? ma v dd ana (intx mode) 2 ? 5 ? ma v dd dig (in rx mode) 2,7,9 ? 13 ? ma v dd dig (in tx mode) 2,8,9 ? 7 ? ma v dd synth 2,7,8 ? 20 ? ma v dd rx1 2 ? 73 ? ma v dd rx2 2 ? 33 ? ma v dd tx 2 ? 81 ? ma ac parameters clock input 'high' pulse width 3 20 ? ? ns 'low' pulse width 3 20 ? ? ns signal amplitude 0.5 ? ? v p-p input impedance (at 19.2 mhz) 20 ? ? k c interface input logic "1" level 4, 5 80% ? ? v ddh input logic "0" level 4, 5 ? ? 20% v ddh input leakage current (vin = 0 to v ddh ) 2, 4, 5 -5.0 ? +5.0 a input capacitance 4, 5 ? 10 ? pf output logic "1" level (l oh = 120 a) 5 90% ? ? v ddh output logic "0" level (l ol = 360 a) 5, 6 ? ? 10% v ddh 'off' state leakage current (vout = v ddh ) 2, 6 ? ? 10 a notes: 2. tamb = 25c, not including any current drawn from the device pins by external circuitry. 3. timing for the external input to the clock pin. 4. wrn, rdn, csn, a0 - a5 pins. 5. d0 - d7 pins. 6. irqn pin. 7. for 420mhz rx operation, main adc and auxdac1 enabled, 14.4mhz reference. 8. for 425mhz tx operation, sending a pr bs sequence (tso). main dac, auxdac0 and auxdac1 enabled, 14.4mhz reference. 9. for 9.6k bits/sec, bt=0.5 operation with a 14.4mhz clock (i.e. internal clock pll enabled, see 5.3.10), using an ev9900a evaluation kit.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 91 d/990/6 notes min. typ. max. unit ac parameters rx 1 st mixer input frequency range 200 ? 950 mhz local oscillator frequency range 11 700 ? 2000 mhz if output frequency 44 45 46 mhz gain 10 ? 0.5 ? db input third order intercept point ? +8 ? dbm noise figure 17,18 13 db image rejection ? 33 ? db output impedance ? 350 // 4.5 ? / pf output noise voltage 13 ? 4.9 ? nv/ hz half if response 15 ? 60 ? db rx if stages input frequency range 44 45 46 mhz input third order intercept (max gain) 16 ? -30 ? dbm input impedance ? 4000 / 3.7 ? / pf noise figure ? 7 ? db maximum gain (max agc) 16 ? 63 ? db minimum gain (min agc) 16 ? 18 ? db agc step size ? 15 ? db agc step size accuracy ? 1 ? db selectivity at 1 to 10 mhz 50 ? ? db selectivity at 1.92 mhz (adc alias) 12 65 ? ? db i/q image rejection ? 30 ? db local oscillator range 14 176 180 184 mhz rssi output digital notes: 10. gain shown is for a matched 50 source, however the input is high impedance and transformer or equivalent voltage step-up circ uits can be used to achieve a higher gain figure. if such arrangements are used input third order intercept point will be degraded. 11. a divide by 2 is provided within the ic. 12. adc alias dependant on clock bit rate (see section 6.5.1). 13. level predicted from simulation. 14. ic contains divide by 4. 15. test with receiver frequency of 867mhz, if of 45mhz giving half if response at 889.5mhz (i.e. 867 + 22.5mhz). 16. measured with 47 ohm resistor between pin ifin and ground. 17. noise figure quoted is based on measured data when evaluated as a dsb noise figure however it will be noted that the input match pr ovides a degree of selectivity so the result is something approaching the ssb noise figure of the mixer. the result is the correct (practical) value for use in most receiver designs. 18. configuration as figure 7.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 92 d/990/6 notes min. typ. max. unit ac parameters (continued) tx offset mixer input frequency range 200 ? 950 mhz local oscillator frequency range 24 700 ? 2000 mhz if output frequency 40 ? 90 mhz input level -57 ? +10 dbm tx limiter/modulator/phase detector input frequency range 40 ? 90 mhz combined rms phase error ? 1.5 ? deg combined peak phase error ? 4.5 ? deg charge pump output current ? 1.0 ? ma normal input level 22 -35 ? -10 dbm total limiting range 22 -91 ? -10 dbm if input frequency 23 160 ? 180 mhz tx offset-phase locked loop minimum input level 45mhz if 20 ? -57 ? dbm minimum input level 90mhz if 20 ? -57 ? dbm maximum input level ? ? +10 dbm lock time 21 ? 200 ? s notes: 20. input value at tx fb pin (tx o- pll mixer input); tx attenuator setting = 0db 21. lock time depends on loop filter, tx if frequency, vco tuning gain etc. value stated measured for 45mhz with 250khz tx loop bandwidth. 22. normal input level is the range over whic h phase error performance is specified. the total limiting range is an extended range, the lo wer end of which is intended to allow the tx loop to ?lock up? during power up. 23. tx lo chain has selectable divide by 2 or divide by 4. 24. a divide by 2 is provided within the ic.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 93 d/990/6 notes min. typ. max. unit auxiliary adc resolution ? 10 ? bits input range 30 ? ? 10 to 90 % v dd ana auxiliary dac 31 resolution ? 10 ? bits output range ? ? 10 to 90 % v dd ana phase locked loop reference input frequency 34 ? 6 to 20 ? mhz level 32 0.5 ? ? vp-p divide ratios 33 1 ? 8192 main rf synthesizer comparison frequency ? ? 500 khz input frequency range 600 ? 2000 mhz input level -20 ? -10 dbm divide ratios 1024 ? 104857 5 charge pump current ? 2.5 ? ma normalised ssb phase noise ? -152 ? dbc/hz aux if synthesizer comparison frequency ? 100 600 khz input frequency range 150 ? 250 mhz input level -20 ? -10 dbm divide ratios 2 ? 16383 charge pump current ? 2.5 ? ma normalised ssb phase noise ? -144 ? dbc/hz notes: 30. aux adc 2 and 3 have uncommitted op-amps on the input. 31. aux dac 0 provides a power ramp for the pa, based on a user-programmable ramp table. aux dac 1 should be connected to vcxo (or vctcxo) for afc control. 32. sine wave or clipped sine wave. 33. separate dividers provided for rf and if pll?s. 34. 14.4 mhz and 19.2 mhz are commonly used.
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 94 d/990/6 operating characteristics (continued) timing diagrams figure 46 c parallel interface timings
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 95 d/990/6 for the following conditions unless otherwise specified: clock frequency = 19.2mhz, v ddh = 3.0v to 3.6v, t amb = -40c to +85c. notes min. typ. max. unit parallel interface timings (ref. figure 46) t acsl address valid to csn low time 0 ? ? ns t ah address hold time 10 ? ? ns t csh csn hold time 0 ? ? ns t cshi csn high time 6 ? ? clock cycles t csrwl csn to wrn or rdn low time 0 ? ? ns t dhr read data hold time 0 ? ? ns t dhw write data hold time 0 ? ? ns t dsw write data setup time 90 ? ? ns t rhcsl rdn high to csn low time (write) 0 ? ? ns t racl read access time from csn low 40 ? ? 175 ns t rarl read access time from rdn low 40 ? ? 145 ns t rl rdn low time 200 ? ? ns t rx rdn high to d0-d7 3-state time ? ? 50 ns t whcsl wrn high to csn low time (read) 0 ? ? ns t wl wrn low time 200 ? ? ns notes: 40. with 30pf max to v ss on d0 - d7 pins. data valid at greater of: t rarl + t csrwl or t racl .
gmsk packet data modem and rf transceiver cmx990 ? 2008 cml microsystems plc 96 d/990/6 7.2 packaging notes: 1. in this device, the underside of the q1 package should be electrica lly connected to the analogue ground. the circuit board should be designed so that no unwanted short circuits can occur. 2. as package dimensions may change after publication of this datasheet, it is recommended that you check for the latest packaging information from t he datasheets page of t he cml website: [ www.cmlmicro.com]. figure 47 q1 mechanical outline: order as part no. CMX990Q1
gmsk packet data modem and rf transceiver cmx990 handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circu it patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of test ing every product shipped using calibrated test equipment to ensure compliance with thi s product specification. specific testing of all circuit parameters is not necessarily performed.

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